Senior ASIC Validation & Bring-Up Engineer

Cisco Systems, Inc.; San Jose (CA); On-site; USD 170,000 - 290,000; Full time

Job summary

Cisco Systems, Inc. in San Jose seeks a Post-Silicon Validation Engineer to join the Silicon One team responsible for bring-up, validation, and performance analysis of ASICs.

You will collaborate with RTL, firmware, and system teams to extend validation infrastructure, scripts, and test suites, driving quality from pre-silicon to post-silicon readiness, and contribute to fault isolation and yield improvement.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or equivalent with relevant post-silicon experience.
• Experience with ASIC bring-up, debug, and validation in hardware platforms.
• Fluency in C, Python and validation scripting for automation.

Responsibilities

• Plan and set up Silicon Bring-up infrastructure, including system boot, initialization, and Power-On of ASICs.
• Root-cause functional and electrical issues with design, verification, and board teams.
• Prepare Validation Test plan and execute functional/performance tests on IP, subsystem and full-chip.
• Extend post-silicon validation infrastructure, automation, and test suites with efficient results capture and regression.
• Apply lab instrumentation expertise (osciloscopes, analyzers, traffic generators) for validation.
• Collaborate with RTL, DFT, ATE, firmware, and system teams to ensure smooth pre- to post-silicon transition.
• Provide feedback on test escapes, yield issues, and silicon errata influencing silicon revisions.

Skills

ASIC bring-up

C, Python scripting

Validation automation

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

Oscilloscopes

Test equipment

Job description

Cisco Systems, Inc. in San Jose seeks a Post-Silicon Validation Engineer to join the Silicon One team responsible for bring-up, validation, and performance analysis of ASICs.

You will collaborate with RTL, firmware, and system teams to extend validation infrastructure, scripts, and test suites, driving quality from pre-silicon to post-silicon readiness, and contribute to fault isolation and yield improvement.