Lead Silicon Bring-Up & Validation for Next-Gen FPGA

Lattice Semiconductor; San Jose (CA); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Competitive compensation

Equity

Benefits

Collaborative culture

Job summary

Lattice Semiconductor is seeking a skilled validation engineer in San Jose, CA, to validate and characterize next-generation FPGAs. The role involves hands-on work with board-level bring-up and testing of high-speed interfaces.

Qualified candidates should have at least 5 years of experience, a degree in Electrical Engineering, and proficiency in tools like Verilog, JMP, and R. Join a leading company known for innovative low-power FPGA solutions.

Qualifications

• 5+ years in silicon or post-silicon validation.
• Hands-on expertise in high-speed interfaces like PCIe and USB.
• Proficiency in scripting for test automation.

Responsibilities

• Lead board-level bring-up and validation of FPGA IPs.
• Develop validation plans from silicon arrival through production release.
• Characterize datasheet parameters and analyze statistical data.

Skills

High-speed interface characterization

Signal integrity

Problem-solving

Communication

Education

Degree in Electrical Engineering

Tools

Verilog/VHDL

FPGA development tools

JMP

R

Job description

Lattice Semiconductor is seeking a skilled validation engineer in San Jose, CA, to validate and characterize next-generation FPGAs. The role involves hands-on work with board-level bring-up and testing of high-speed interfaces.

Qualified candidates should have at least 5 years of experience, a degree in Electrical Engineering, and proficiency in tools like Verilog, JMP, and R. Join a leading company known for innovative low-power FPGA solutions.