Senior Silicon Validation Engineer (FPGA/IP)

Lattice; San Jose (CA); On-site; USD 198,720 - 242,880; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Job summary

Lattice in San Jose is seeking a Silicon Validation Engineer to validate and characterize building blocks in FPGA, ensuring design intent functionality and performance. This role requires strong expertise in high-speed Serdes, Verilog/VHDL, and test automation.

The ideal candidate will develop testing logic, lead validation efforts, and support product release issues. A degree in Electrical Engineering and significant experience in the field are essential. Join us to be part of cutting-edge projects!

Qualifications

• 8+ years of experience in silicon design validation.
• Strong desire to pursue an engineering career.
• Proficiency in high-speed board design.

Responsibilities

• Validate and characterize various IPs from silicon arrival to production.
• Develop validation and characterization plans.
• Drive new silicon product validation and debug.

Skills

High Speed Serdes Interface characterization

Verilog/VHDL

Test automation development

Statistical analysis concepts

Device characterization equipment

Education

Electrical Engineering degree

Tools

BERT

VNA

Oscilloscopes

Job description

Lattice in San Jose is seeking a Silicon Validation Engineer to validate and characterize building blocks in FPGA, ensuring design intent functionality and performance. This role requires strong expertise in high-speed Serdes, Verilog/VHDL, and test automation.

The ideal candidate will develop testing logic, lead validation efforts, and support product release issues. A degree in Electrical Engineering and significant experience in the field are essential. Join us to be part of cutting-edge projects!