Silicon Validation Tech Lead – Next-Gen FPGA

Lattice Semiconductor; San Jose (CA); On-site; USD 150,000 - 180,000; Full time

Benefits offered by this job

Competitive compensation

Equity

Benefits

High-ownership culture

Job summary

Lattice Semiconductor is searching for a Technical Leader in San Jose to own the validation strategy for next-generation FPGA silicon. This role demands in-depth experience and the ability to guide a team through successful silicon brings-up, characterization, and release.

The ideal candidate will possess over 8 years of validation experience, expertise in high-speed interfaces, and the capabilities to communicate effectively with cross-functional teams. Competitive compensation and benefits are offered in this full-time onsite position.

Qualifications

• 8+ years in post-silicon or silicon design validation.
• Proven tech lead experience, guiding a team.

Responsibilities

• Lead validation strategy for FPGA IPs.
• Drive new silicon bring-up end-to-end.
• Author test logic RTL and automation frameworks.

Skills

High-speed interface characterization

Signal integrity

FPGA development tools

Test automation in Python

Proficiency in Verilog/VHDL

Statistical analysis

Communication skills

Education

Degree in Electrical Engineering or related field

Tools

BERT

VNA

Oscilloscopes

Job description

This isn't a contributor role with a senior label on it. We're looking for a technical leader who owns the validation strategy for next-generation FPGA silicon — someone who's been in the lab long enough to know what questions to ask before the silicon even arrives and experienced enough to lead a team through the answers

You'll drive bring-up, characterization, and release of cutting‑edge FPGA IPs while serving as the technical anchor across design, verification, manufacturing, and test team

What You’ll Do

• OwnDefine and lead validation strategy for FPGA IPs — SERDES (PMA/PCS), DDR (DDR4/DDR5/LPDDR4), DPHY, PLL, DSP, MIPI, Fabric,
• I/ODrive new silicon bring-up end-to-end — from first power‑on through datasheet sign‑off and production rele
• aseLead a small team of validation engineers as tech lead — set direction, review plans, unblock iss
• uesDevelop high-coverage characterization plans; own statistical data analysis and datasheet preparat
• ionAuthor test logic RTL and automation frameworks in Python/P
• erlBe the central cross‑functional resource as silicon moves from arrival to rele
• aseSupport customer escalations post‑release — own the issue, drive the

What You Bring

• ing8+ years in post‑silicon or silicon design validat
• ionDegree in Electrical Engineering or related fi
• eldProven tech lead experience — you've guided a team, not just contributed to
• oneDeep expertise in high‑speed interface characterization — PCIe, Ethernet, MIPI D‑PHY, USB, DisplayPort/HDMI, JESD204, SDI/CoaXpr
• essStrong signal integrity and high‑speed board design/debug ski
• llsProficiency in Verilog/VHDL and FPGA development to
• olsTest automation in Python or Perl — you build frameworks, not just scri
• ptsExpert‑level bench proficiency — BERT, VNA, Oscilloscopes, Protocol Analyz
• ersStatistical analysis experience — JMP, R, or equival
• entSharp communicator across engineering, manufacturing, and customer‑facing te

Nice to Have

• aveExperience with FPGA emulation or prototyping environme
• ntsBackground in datasheet preparation and IP release methodol

Location

San Jose, CA — Onsite, Full‑Time

Why Lat tice? We're the low power FPGA leader — and our silicon validation team is where product quality is won or lost. You won't be inheriting a steady‑state program. You'll be shaping

one.Competitive compensation | Equity | Benefits | High-ownership cu

Lattice Semiconductor is an equal opportunity employer. We encourage candidates from diverse backgrounds to