FPGA Engineering Manager: Lead Cutting-Edge Memory Test

LitePoint; Tualatin (OR); On-site; USD 172,000 - 232,000; Full time

Job summary

Teradyne’s Memory Test Division (MTD) seeks a hands-on FPGA Engineering Manager to oversee cutting-edge memory test solutions. This role combines technical leadership with project management to deliver high-quality devices that support advanced memory technologies.

You will lead a small team of 4 to 6 engineers, guide RTL design, timing closure, and lab validation, and collaborate with hardware, software, and firmware teams to ensure seamless integration.

Qualifications

• 12+ years in Digital ASIC or FPGA design
• 5+ years as FPGA/ASIC project lead driving multiple projects
• RTL coding experience (Verilog preferred)
• Cadence or similar digital simulation tools
• Static timing analysis experience
• Experience with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES
• Experience with AMD or Altera FPGAs and development tools (Vivado/Quartus)
• Experience with lint, CDC
• Experience with bug tracking tools and CI
• Familiarity with UVM and digital verification methodologies
• Experience with project scheduling tools
• Excellent presentation and communication skills

Responsibilities

• Plan, prioritize, and manage multiple FPGA development projects within budget and scope
• Represent the FPGA team on project core teams and program reviews
• Provide support for sustaining issues
• Collaborate with hardware, software, and firmware engineers for seamless integration
• Recruit, onboard, and retain top engineering talent
• Set goals and conduct regular performance conversations for a team of 4–6 engineers
• Contribute to FPGA team process improvement initiatives
• Provide hands-on technical guidance on FPGA architectures, designs, and specifications
• Active participation in RTL design, synthesis, timing closure, and lab validation

Skills

RTL coding

Verilog

Cadence

Vivado/Quartus

Project leadership

PCIe

DDR5

AXI

SerDes

UVM

Synthesis & timing

Lab validation

Education

B.S./M.S. in Electrical Engineering

Tools

AMD/Altera FPGA tools

Vivado/Quartus

Job description

Teradyne’s Memory Test Division (MTD) seeks a hands-on FPGA Engineering Manager to oversee cutting-edge memory test solutions. This role combines technical leadership with project management to deliver high-quality devices that support advanced memory technologies.

You will lead a small team of 4 to 6 engineers, guide RTL design, timing closure, and lab validation, and collaborate with hardware, software, and firmware teams to ensure seamless integration.