FPGA/ASIC Design Engineer – Space-Grade SoC

Starlink; Irvine (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

SpaceX in Irvine, CA is seeking a motivated FPGA/ASIC Design Engineer (Silicon Engineering) to design SoC blocks for Starlink. You will work across architecture to validation teams, delivering high‑reliability FPGA/ASIC solutions for space and ground systems.

The ideal candidate holds a Bachelor’s in EE/CE/CS/Physics and 1+ years RTL design with SystemVerilog/Verilog/VHDL, plus experience with HDL tools and DSP datapaths. This is a full‑time, on‑site role with ITAR compliance and strong benefits.

Qualifications

• Bachelor’s degree in EE/CE/CS/Physics is required.
• 1+ years RTL design with SystemVerilog/Verilog/VHDL.
• Experience with HDL tools and DSP datapaths.

Responsibilities

• Design and implement FPGA/ASIC RTL blocks as part of SoC for Starlink.
• Collaborate across architecture, implementation, and validation teams.
• Deliver high-reliability FPGA/ASIC solutions for space and ground systems.

Skills

RTL design

SystemVerilog/Verilog/VHDL

DSP datapaths

HDL tools

Education

Bachelor's degree in EE/CE/CS/Physics

Tools

HDL tools

Job description

SpaceX in Irvine, CA is seeking a motivated FPGA/ASIC Design Engineer (Silicon Engineering) to design SoC blocks for Starlink. You will work across architecture to validation teams, delivering high‑reliability FPGA/ASIC solutions for space and ground systems.

The ideal candidate holds a Bachelor’s in EE/CE/CS/Physics and 1+ years RTL design with SystemVerilog/Verilog/VHDL, plus experience with HDL tools and DSP datapaths. This is a full‑time, on‑site role with ITAR compliance and strong benefits.