ASIC/FPGA SoC Design Engineer (Space/Comm)

Starlink; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Medical coverage

Vision and dental

401(k) plan

Disability insurance

Life insurance

Paid parental leave

Stock purchase plan

Paid vacation and holidays

Job summary

SpaceX is seeking an ASIC Design Engineer (Silicon Engineering) in California to design ASICs and FPGAs for Starlink, developing next-generation chips for space and ground infrastructures.

You will work with cross-disciplinary teams, implement complex SoC blocks in Verilog/SystemVerilog, optimize for power and area, and contribute to a full design lifecycle with strong lab bring-up and validation, and collaboration with software teams.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering, Computer Science, or Physics.
• 1+ years of RTL design experience with SystemVerilog/Verilog/VHDL.
• Strong foundation in electrical engineering fundamentals.

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks using Verilog/SystemVerilog.
• Optimize designs for power, performance and area.
• Participate in the full ASIC/FPGA design lifecycle from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams.
• Contribute to continual improvements by building physical and digital tools to analyze data collected on orbit and in the lab.
• Engage in high-level architectural design for test systems to support FPGA/ASIC validation and interoperability.
• Collaborate with software engineers in developing production software for your designs.

Skills

RTL Design

SystemVerilog

Verilog

VHDL

Python

C/C++

Bash

DSP / modem design

EDA tools

AXI/AHB/APB protocols

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics

Master’s in Electrical/Computer Engineering or related field

Tools

HDL simulators (VCS, Questa, IES)

Spyglass

Xilinx Vivado

Altera Quartus II

Job description

SpaceX is seeking an ASIC Design Engineer (Silicon Engineering) in California to design ASICs and FPGAs for Starlink, developing next-generation chips for space and ground infrastructures.

You will work with cross-disciplinary teams, implement complex SoC blocks in Verilog/SystemVerilog, optimize for power and area, and contribute to a full design lifecycle with strong lab bring-up and validation, and collaboration with software teams.