Founding Physical Design Lead for AI ASICs

OHO Group (Lithuania); San Francisco (CA); Sur place; USD 180 000 - 320 000; Plein temps

Résumé du poste

OHO Group is seeking a Physical Design Lead and Founding Engineer for a stealth semiconductor startup in AI silicon. You will own end-to-end physical implementation for custom ASICs, setting up architecture and leading a growing team of engineers.

You will deploy AI-driven design-optimisation engines to improve macro placement, clock and power networks, and tackle high-speed, high-density layouts. This is a hands-on leadership role requiring deep experience with STA/DRC/LVS/EM/IR on advanced

Qualifications

• 5–10 years of physical-design experience with tape-out of large SoCs or compute subsystems.
• Hands-on with AI-enabled design-optimisation tools in production flows.
• Strong AI literacy within the implementation workflow for optimisations.
• Expertise in physical sign-off: STA, DRC, LVS, EM/IR on advanced nodes.

Responsabilités

• Lead deployment of AI-driven design-optimisation engines for macro placement, clock/power networks.
• Address physical-design challenges for AI workloads, including IR-drop and thermal-density mitigation.
• Own end-to-end physical implementation across custom ASICs.
• Build and grow a team, serving as a technical lead.

Connaissances

Physical design

AI-enabled design tools

AI in design workflow

Physical sign-off (STA/DRC/LVS/EM/IR)

Outils

EDA tools

Description du poste

OHO Group is seeking a Physical Design Lead and Founding Engineer for a stealth semiconductor startup in AI silicon. You will own end-to-end physical implementation for custom ASICs, setting up architecture and leading a growing team of engineers.

You will deploy AI-driven design-optimisation engines to improve macro placement, clock and power networks, and tackle high-speed, high-density layouts. This is a hands-on leadership role requiring deep experience with STA/DRC/LVS/EM/IR on advanced