Senior Digital Design Engineer for High-Throughput AI ASICs

Olix Computing; Austin (TX); On-site; USD 140,000 - 230,000; Full time

Benefits offered by this job

Equity

Ownership

Proximity Bonus

Retirement Plan

Job summary

Olix Computing seeks Senior/Staff Digital Design Engineers to own end‑to‑end high‑speed data processing silicon from modelling to RTL and silicon bring‑up. You will join a multidisciplinary team where digital, optical and mixed‑signal domains intersect to push AI hardware performance.

The role covers architecture, RTL development, FPGA prototyping, MATLAB/Simulink modelling and strong collaboration across hardware and software teams, with mentorship of junior engineers.

Qualifications

• 7+ years of hands‑on digital design for high‑performance ASICs/SoCs.
• Experience with multi‑hundred‑MHz to multi‑GHz clock domains and high‑speed IP integration.
• Strong HDL expertise and verification methodology.

Responsibilities

• Architect, design and implement high‑throughput digital pipelines in CMOS nodes demarcating multi‑GSPS input data.
• Prototype and iterate in FPGA real‑time demos and feed learnings into ASIC.
• Model algorithms in MATLAB/Simulink to validate concepts.
• Own RTL development (SystemVerilog/Verilog/VHDL) including synthesis and formal verification.
• Analyze PPA and optimize bandwidth‑per‑watt with innovative techniques.
• Collaborate with optical hardware and software teams to optimise interfaces.
• Mentor junior engineers and lead design reviews.

Skills

CMOS Digital Design

RTL/Verilog/VHDL

FPGA Prototyping

SystemVerilog

High-Speed Interfaces

MATLAB/Simulink

Clock-Domain Crossing

EDA Flows

Tools

Xilinx/AMD FPGA

Intel FPGA

ASIC/SoC toolchain

Job description

Olix Computing seeks Senior/Staff Digital Design Engineers to own end‑to‑end high‑speed data processing silicon from modelling to RTL and silicon bring‑up. You will join a multidisciplinary team where digital, optical and mixed‑signal domains intersect to push AI hardware performance.

The role covers architecture, RTL development, FPGA prototyping, MATLAB/Simulink modelling and strong collaboration across hardware and software teams, with mentorship of junior engineers.