Physical Design Lead

Oho Group; San Francisco (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

OHO Group seeks a Physical Design Lead to own ASIC implementation from RTL to GDS. You will drive synthesis, floorplanning, placement, CTS, routing and timing closure, pushing PPA gains while preserving signoff quality.

Lead automation with Python/Tcl and apply AI-assisted tooling to streamline workflows, combining hands-on design ownership with leadership in a fast-evolving AI-infused semiconductor space.

Qualifications

• 5+ years of ASIC physical-design experience.
• Hands-on ownership of designs through tapeout.
• Broad implementation and signoff expertise with PPA trade-offs.
• Strong scripting skills and experience improving EDA flows.
• Practical experience using AI tools in engineering with validation.

Responsibilities

• Lead ASIC implementation from RTL through to GDS.
• Own synthesis, floorplanning, placement, clock-tree synthesis, routing and timing closure.
• Drive power, performance and area improvements while maintaining signoff quality.
• Resolve timing, physical verification and power-integrity issues.
• Build Python and Tcl automation and apply AI-assisted tooling to implementation workflows.

Skills

ASIC design

Scripting

AI in engineering

EDA flows

Tapeout ownership

Tools

Python

Tcl

EDA tools

Job description

Physical Design Lead – ASIC Implementation

Take ownership of silicon delivery and improve how it gets done.

Our client working at the intersection of AI and semiconductor engineering is looking for a Physical Design Lead to own implementation and bring rigorous engineering judgment to increasingly automated design workflows.

This is a hands-on technical leadership role, combining responsibility for physical-design quality with the opportunity to improve the tools and methods behind it.

What you’ll do:

• Lead ASIC implementation from RTL through to GDS.
• Own synthesis, floorplanning, placement, clock-tree synthesis, routing and timing closure.
• Drive power, performance and area improvements while maintaining signoff quality.
• Resolve timing, physical verification and power-integrity issues.
• Build Python and Tcl automation and apply AI-assisted tooling to implementation workflows.

What you’ll bring:

• Strong ASIC physical-design experience, typically 5+ years.
• Hands-on ownership of designs taken through tapeout.
• Broad implementation and signoff expertise, with clear judgment around PPA trade-offs.
• Strong scripting skills and experience improving EDA flows.
• Practical experience using AI tools in engineering, with careful validation of their outputs.

Reinforcement learning or AI-accelerator implementation experience would be useful additional strengths.

You’ll help deliver working silicon while shaping more effective implementation workflows.