Founding Physical Design Engineer

Oho Group; San Francisco (CA); On-site; USD 180,000 - 320,000; Full time

Job summary

OHO Group is seeking a Physical Design Lead and Founding Engineer for a stealth semiconductor startup in AI silicon. You will own end-to-end physical implementation for custom ASICs, setting up architecture and leading a growing team of engineers.

You will deploy AI-driven design-optimisation engines to improve macro placement, clock and power networks, and tackle high-speed, high-density layouts. This is a hands-on leadership role requiring deep experience with STA/DRC/LVS/EM/IR on advanced

Qualifications

• 5–10 years of physical-design experience with tape-out of large SoCs or compute subsystems.
• Hands-on with AI-enabled design-optimisation tools in production flows.
• Strong AI literacy within the implementation workflow for optimisations.
• Expertise in physical sign-off: STA, DRC, LVS, EM/IR on advanced nodes.

Responsibilities

• Lead deployment of AI-driven design-optimisation engines for macro placement, clock/power networks.
• Address physical-design challenges for AI workloads, including IR-drop and thermal-density mitigation.
• Own end-to-end physical implementation across custom ASICs.
• Build and grow a team, serving as a technical lead.

Skills

Physical design

AI-enabled design tools

AI in design workflow

Physical sign-off (STA/DRC/LVS/EM/IR)

Tools

EDA tools

Job description

Physical Design Lead - Founding Engineer - Stealth Startup

A fast-growing semiconductor startup working in the AI silicon space is developing an AI-driven chip-design platform. The team combines deep expertise across AI, semiconductor architecture, physical design and chip development, with a focus on building highly automated approaches to custom silicon development.

They're looking for an engineering leader to drive physical implementation for custom ASICs. This is an end-to-end technical leadership role setting up architecture, collaborating with the wider team and eventually building out your own too.

Core Responsibilities

• Lead deployment of AI-driven design-optimisation engines to automate macro placement, optimise clock and power distribution networks, and maximise PPA.
• Address physical-design challenges associated with AI workloads, including dynamic IR-drop, thermal-density mitigation and multi-GHz clock-tree synthesis.
• Own end-to-end physical implementation across custom ASICs.
• Build and grow out a team, serving as a technical lead.

Required Qualifications

• 5–10 years of physical-design experience, with a track record of taking complex, large-die SoCs or compute subsystems through tape-out.
• Hands-on experience integrating AI-enabled design-optimisation tools into production implementation flows.
• Strong AI literacy within the implementation workflow, particularly optimisations relevant to EDA and layout density.
• Proven expertise in physical sign-off, including STA, DRC, LVS and EM/IR on advanced process nodes.

This is one of the most unique and in-demand roles going at the moment - if you're interested.