Senior ASIC Lead — Mixed-Signal & Tapeout

Teradyne; California; On-site; USD 192,000 - 308,000; Full time

Job summary

Teradyne's Silicon Technology Engineering team is seeking an experienced Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment systems.

The ideal candidate will coordinate cross-functional engineering teams, external partners, and stakeholders while balancing schedule, cost, and quality to ensure successful tapeout readiness and silicon bring-up.

Qualifications

• Strong leadership and program-management skills required.
• Experience leading complex ASIC developments from concept to production."

Responsibilities

• Lead cross-functional teams including architecture, analog/digital design, verification, and operations.
• Coordinate with external partners and foundry vendors.
• Ensure schedule, cost, quality, and tapeout readiness objectives are met.

Skills

Leadership

Education

BSEE/MSEE

Job description

Teradyne's Silicon Technology Engineering team is seeking an experienced Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment systems.

The ideal candidate will coordinate cross-functional engineering teams, external partners, and stakeholders while balancing schedule, cost, and quality to ensure successful tapeout readiness and silicon bring-up.