Senior ASIC Verification Lead - Pre-silicon & Tapeout (Remote)

Tensordyne; United States; Remote; USD 180,000 - 280,000; Full time

Benefits offered by this job

Meals, snacks, drinks

Bonusly awards

Job summary

Tensordyne is seeking a senior ASIC verification leader to steer all phases of verification for our next-generation AI inference processors. You will ensure pre-silicon correctness for multi-million gate ASICs and collaborate with SoC IP blocks to meet performance goals in data center environments.

You will mentor verification engineers, drive test plans, scalability of testbenches, and coordinate sign-off criteria while working in a fast-paced startup culture that values collaboration and

Qualifications

• 15+ years of ASIC verification experience spanning full cycle and post-silicon validation.
• Expert in System Verilog, UVM, Constraint Randomization, Functional Coverage.
• Experience in C/C++ or System-C.
• Deep understanding of object oriented programming, constrained random stimulus, and coverage driven verification.
• Verification experience of high-speed interfaces (PCIe, Ethernet, DDR/HBM, SerDes).
• Scripting experience (Python, Perl, TCL, shell) highly desirable.
• Interest in AI architectures for convolution, transformer workloads.
• Self-starter in a dynamic start-up environment.
• B.S. (M.S. preferred) in Electrical or Computer Engineering.

Responsibilities

• Lead verification planning from architecture through tapeout.
• Develop block-level, sub-system and full-chip verification environments and tests.
• Establish reusable verification methodologies and scale testbenches.
• Collaborate with design/architecture to meet functional and performance goals.
• Triage and debug issues and drive signoff criteria.
• Mentor verification engineers and guide test planning.
• Perform diagnostic and post-silicon validation tests.

Skills

SystemVerilog

UVM

Constraint Randomization

Functional Coverage

C/C++

SystemC

Object Oriented Programming

PCIe

Ethernet

DDR/HBM

SerDes

Python

ARM/RISC-V verification

Education

B.S. in Electrical or Computer Engineering

M.S. preferred

Tools

Arm/RISC-V

SystemVerilog simulators

Job description

Tensordyne is seeking a senior ASIC verification leader to steer all phases of verification for our next-generation AI inference processors. You will ensure pre-silicon correctness for multi-million gate ASICs and collaborate with SoC IP blocks to meet performance goals in data center environments.

You will mentor verification engineers, drive test plans, scalability of testbenches, and coordinate sign-off criteria while working in a fast-paced startup culture that values collaboration and