Vice President of ASIC Engineering

Architect Labs; Palo Alto (CA); On-site; USD 300,000 - 600,000; Full time

Benefits offered by this job

Equity

Competitive compensation

Job summary

Architect Labs is seeking a visionary leader to own the ASIC methodology and end-to-end delivery of ambitious AI compute silicons, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. You will build a faster, AI-native flow with data-driven feedback to accelerate design iterations and engineering productivity.

You will lead a world-class team, set uncompromising PPA and silicon quality standards, and personally steer critical technical and execution

Qualifications

• Repeated tapeout success on complex ASIC/SoC programs, ideally at advanced nodes.
• End-to-end ASIC mastery: RTL, verification, synthesis, timing, physical, signoff, bring-up.

Responsibilities

• Own the ASIC methodology and end-to-end delivery from RTL through tapeout.
• Lead a world-class silicon engineering team and drive key technical decisions.
• Push for automation, ML/AI-assisted EDA, and scalable engineering infrastructure.

Skills

ASIC leadership

RTL design

Functional verification

Synthesis

Timing closure

DFT

Team building

Cross-functional leadership

Tools

EDA tools

Automation scripting

Job description

About Architect Labs

Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.

What You'll Do

Own the ASIC methodology and end-to-end delivery of ambitious AI compute silicons, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. Build a fundamentally faster, AI-native chip-development flow, using automation, intelligent agents, and data-driven feedback loops to accelerate design iteration, verification, closure, and engineering productivity. Lead a world-class team, set an uncompromising bar for PPA and silicon quality, and personally drive the most consequential technical and execution decisions.

What We'd Like to See

• Repeated tapeout success: Direct leadership of multiple complex, production-volume ASIC or SoC programs, ideally at advanced process nodes.

• End-to-end ASIC mastery: Deep expertise spanning RTL, functional verification, synthesis, timing closure, physical implementation, DFT, signoff, and silicon bring-up.

• Methodology innovator: A track record of transforming design flows through automation, ML/AI-assisted EDA, verification productivity, or scalable engineering infrastructure—not merely operating established processes.

• Execution excellence: A demonstrated ability to deliver demanding programs with strong first-silicon outcomes and disciplined engineering tradeoffs.

• Elite team builder: A record of recruiting, developing, and leading world-class silicon engineers and technical leaders.

• Hands-on leadership: Credibility to resolve difficult cross-functional engineering problems personally while building processes that scale.

What We Offer

Competitive compensation and meaningful equity, ownership of critical silicon programs, and the chance to build a world-class ASIC organization at the frontier of computing.