Senior ASIC Chip Lead - Cross-Functional Tapeout Champion

Teradyne; Agoura Hills (CA); On-site; USD 192,000 - 308,000; Full time

Benefits offered by this job

medical

dental

vision

Flexible Spending Accounts

retirement savings plans

life and disability insurance

paid vacation & holidays

tuition assistance programs

and more

Job summary

Teradyne’s Silicon Technology Engineering team seeks an experienced Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment (ATE) systems.

This role requires a proven leader who can coordinate cross-functional engineering teams, external partners, and key stakeholders while ensuring technical, schedule, cost, and quality objectives are met.

Qualifications

• BSEE, MSEE, or equivalent with 15+ years of semiconductor industry experience and 5+ years leading complex ASIC developments.
• Proven success leading multiple complex mixed-signal ASICs through architecture, design, verification, tapeout, silicon bring-up, and production.
• Experience managing geographically distributed teams and external design partners.
• Strong program management skills, including schedule planning, risk management, and executive communications.
• Proven ability to lead through influence across multiple engineering disciplines.
• Experience with advanced-node ASIC development preferred.

Responsibilities

• Accountable for successful ASIC execution from concept through production, including schedule, quality, cost, tapeout readiness, and first-pass silicon success.
• Lead cross-functional teams including architecture, analog design, digital design, verification, physical design, package engineering, test, characterization, and operations.
• Partner with system architects and engineering leaders to define ASIC architecture, technical tradeoffs, execution strategy, and product requirements.
• Drive schedule development, critical-path management, milestone tracking, and risk mitigation.
• Conduct regular program reviews and provide status updates to engineering and executive leadership.
• Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners.
• Resolve technical and program conflicts while balancing quality, cost, and schedule objectives.
• Drive tapeout readiness reviews and silicon bring-up planning.
• Develop staffing plans and identify resource gaps throughout the project lifecycle.

Skills

ASIC leadership

Program management

Cross-functional leadership

Stakeholder communication

Education

BSEE, MSEE, or equivalent

Tools

EDA tools

Job description

Teradyne’s Silicon Technology Engineering team seeks an experienced Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment (ATE) systems.

This role requires a proven leader who can coordinate cross-functional engineering teams, external partners, and key stakeholders while ensuring technical, schedule, cost, and quality objectives are met.