DFT (Design for Test) Lead

Avacend Inc; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Avacend Inc in California seeks a senior DFT Technical Lead to drive design-for-test features for Silicon One optics. You will lead ATPG, scan compression, memory BIST and memory repair to ensure testable, manufacturable designs.

You will collaborate across the silicon life cycle from pre-silicon design to post-silicon qualification, lead debugging of DFT patterns, integrate 3rd party IPs, and mentor teams while clearly communicating findings.

Qualifications

• Must have DFT leadership experience in silicon/aerospace or telecom environments.
• Hands-on with post-silicon debug of DFT patterns (scan, mbist, boundary scan).
• Experience integrating 3rd party IPs and high-speed macros.

Responsibilities

• Lead development and implementation of DFT features (ATPG, scan compression, memory BIST, memory repair).
• Collaborate across multiple teams through the silicon life cycle from pre-silicon design to post-silicon qualification.
• Drive debugging and root-cause analysis of silicon failures to improve yield and reliability.
• Mentor and train teams on DFT methodologies and best practices.

Skills

DFT Leadership

ATPG

Scan compression

Memory BIST

Memory repair

JTAG protocols

BIST architectures

Third-party IP integration

High-speed digital/analog macros

Post-silicon debugging

DFT methodologies training

Communication skills

Attention to detail

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Tessent

Xcelium

Genus

Tempus/Primetime

Job description

Duration: 12+ months (possibly extending longer based on project timelines)

Candidate Responsibilities:

• Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, MBIST, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Requirements: ("Must have" Qualifications)

• You will be part of the Silicon One optics development organization as a DFT Technical Lead in with a primary focus on Design-for-Test.
• You will develop and implement DFT features - ATPG, scan compression, memory BIST, memory repair to ensure high quality testable and manufactural designs.
• You will contribute to the full product cycle from pre-silicon design to post-silicon debt and production qualification. You will collaborate across multiple teams throughout the silicon life cycle. Starting from implementing DFT features to lead debugging and root cause analysis of silicon failures to improve yield and reliability.
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP’s and high-speed digital/analog macros
• Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, Tempus/Primetime
• At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production
• Strong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production
• Ability to quickly learn new concepts and adapt to evolving technologies
• Excellent communication and presentation skills
• Strong attention to detail and system level understanding of networking and photonic solutions
• Our chips are strategically placed in Silicon one AI infrastructure, powering next generation network devices to support advanced AI workloads.
• Bachelor's or a Master's Degree in Electrical or Computer Engineering required, with at least 8-10 years of experience.