DPU RAS & Debug Architect: Reliability, Trace & Bring-Up

Meta; Menlo Park (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Infrastructure Silicon group is seeking a DPU RAS and Debug Architect to define reliability, availability, and serviceability for our DPUs. You will set FIT-rate targets, design error detection/correction, and build trace, debug, and telemetry systems that support post-silicon and firmware debugging.

You will decide hardware vs firmware vs software boundaries, work with firmware, driver, and RTL teams, and refine architecture to meet PD constraints while enabling DV.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• 8+ years architecting RAS and debug/trace architectures for NIC/DPU or ASICs.
• Experience with memory/RAS concepts and error protection mechanisms (ECC, SECDED, poisoning).
• Experience with on-chip debug/trace architectures (JTAG, CoreSight).

Responsibilities

• Own the RAS and debug architecture for DPUs from early path-finding to silicon bring-up.
• Set FIT-rate targets and budget across memories, logic, interfaces, and links.
• Define error detection, correction, and reporting, and how errors surface to firmware and software.
• Define on-chip trace, telemetry, and crash-state capture for post-silicon and firmware debugging.
• Decide hardware vs firmware vs software boundaries and how devices present to software/firmware.

Skills

RAS architecture

Debug architecture

Fault-tolerance

Performance telemetry

Automation pipelines

Python scripting

SystemVerilog experience

Education

Bachelor's degree in CS/CE

PhD (preferred)

Tools

SystemVerilog

ARM CoreSight

PCIe

JTAG

ETM

Job description

Meta's Infrastructure Silicon group is seeking a DPU RAS and Debug Architect to define reliability, availability, and serviceability for our DPUs. You will set FIT-rate targets, design error detection/correction, and build trace, debug, and telemetry systems that support post-silicon and firmware debugging.

You will decide hardware vs firmware vs software boundaries, work with firmware, driver, and RTL teams, and refine architecture to meet PD constraints while enabling DV.