DPU Performance Architect: Modeling & RTL Validation

Meta; Austin (TX); Presencial; USD 140.000 - 210.000; Jornada completa

Descripción de la vacante

Meta's Infrastructure Silicon organization designs custom silicon that powers data center infrastructure—SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We seek an experienced Performance Architect to drive performance modeling, analysis, and validation of DPU architectures, influencing architecture decisions from early path-finding through RTL validation and silicon correlation.

The role demands deep experience in end-to-end performance analysis, workload characterization, and

Formación

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures.
• Detailed understanding of DPU architectures: network virtualization, storage disaggregation, networking and storage protocols such as RoCE, NVMe, fabric architectures.
• Experience in workload analysis and characterisation, and abstracting key performance features into models for analysis.
• Proficiency in languages for model development (e.g. Python, C/C++, SystemC).

Responsabilidades

• Analyze performance of current and future SmartNIC/IPU/DPU architectures with focus on end-to-end transaction flows, host-to-DPU offloading options, evaluation of SoC architectural options
• Quantify architectural/micro-architectural trade-offs wrt PPA to inform and guide design decisions
• Analyze and characterise DPU workloads to abstract key performance-relevant behaviours and incorporate into representative models and synthetic benchmarks
• Develop and enhance performance models, simulation tools, and methodologies to evaluate future DPU architectures
• Drive RTL performance validation, including development of comprehensive performance test plans, coverage criteria, and correlation of RTL results against architectural models
• Correlate pre-silicon performance projections with post-silicon measurements and drive methodology improvements based on findings

Conocimientos

DPU performance modeling

Performance analysis

Workload analysis

Benchmarking methodologies

Communication with RTL

Educación

Bachelor's degree in Computer Science/Engineering or equivalent

Herramientas

Python

C/C++

SystemC

Descripción del empleo

Meta's Infrastructure Silicon organization designs custom silicon that powers data center infrastructure—SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We seek an experienced Performance Architect to drive performance modeling, analysis, and validation of DPU architectures, influencing architecture decisions from early path-finding through RTL validation and silicon correlation.

The role demands deep experience in end-to-end performance analysis, workload characterization, and