DPU RAS and Debug Architect, Infrastructure Silicon

Meta; Sunnyvale (CA); Presencial; USD 170.000 - 260.000; Jornada completa

Descripción de la vacante

Meta is seeking a DPU RAS and Debug Architect to define reliability, availability, and serviceability architecture for our DPUs. You will set FIT-rate targets, budget them, and decide how errors are detected, corrected, and surfaced to firmware and host software.

You will define the trace, debug, and telemetry infrastructure supporting post-silicon and software/firmware debugging across hardware, firmware, and RTL teams, guiding bring-up from early path-finding through silicon validation.

Formación

• Own the RAS and debug architecture for our DPUs.
• Set FIT-rate targets and budget them across memories, logic, interfaces and links.
• Define error detection, correction, reporting, containment and surface to firmware/host software.
• Define trace, debug and performance-monitoring architecture for post-silicon debug and software/firmware debugging.

Responsabilidades

• Own the RAS and debug architecture for our DPUs - error detection, correction, and reporting, FIT budgeting, and the trace, debug, and telemetry infrastructure - from early path-finding through silicon bring-up
• Set FIT-rate targets from the intended usages and deployment models, and budget them across design components
• Define the error detection, correction, reporting, and containment architecture and how errors are surfaced to firmware, host software, and platform management
• Define the trace, debug, and performance-monitoring architecture for post-silicon debug and for software/firmware debugging - on-chip trace, telemetry, crash capture, and JTAG model

Conocimientos

RAS architecture

Debug architecture

FIT budgeting

Post-silicon debugging

Hardware-software coordination

Telemetry

JTAG

Herramientas

JTAG

Telemetry

Post-silicon debugging tools

Descripción del empleo

# DPU RAS and Debug Architect, Infrastructure SiliconSunnyvale, CA+2 locationsHardware+ 1 moreApply nowMeta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs.We are looking for a Data Processing Unit (DPU) RAS and Debug Architect to define the reliability, availability, and serviceability architecture for our DPU ASICs. You'll set FIT-rate targets from the intended usages and deployment models, define how errors are detected, corrected, and reported, and define the trace, debug, and performance-monitoring architecture that supports both post-silicon debug and software and firmware debugging. You'll decide what belongs in hardware versus firmware versus software, define how the hardware presents itself to firmware and software, and work hand in hand with the firmware, driver, and RTL teams - carrying your designs from early path-finding through implementation and silicon bring-up.---## DPU RAS and Debug Architect, Infrastructure Silicon Responsibilities* Own the RAS and debug architecture for our DPUs - error detection, correction, and reporting, FIT budgeting, and the trace, debug, and telemetry infrastructure - from early path-finding through silicon bring-up* Set FIT-rate targets from the intended usages and deployment models, and budget them across the design - memories, logic, on-chip interfaces, and links* Define the error detection, correction, reporting, and containment architecture -- parity, ECC/SECDED, poisoning and poison propagation, error logging, and how errors are surfaced to firmware, host software, and platform management* Define the trace, debug, and performance-monitoring architecture for post-silicon debug and for software and firmware debugging - on-chip trace, event and counter telemetry, crash and state capture, and the JTAG/debug-access model