Lead DPU I/O Architect for Advanced Infrastructure Silicon

Meta; Austin (TX); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking a Data Processing Unit (DPU) IO Architect to own the I/O subsystem, PCIe, DMA, offload engines, and I/O virtualization for DPUs and NICs. You will define register and programming models, interfaces, and how hardware, firmware, and software interact.

You will work with firmware, driver, and RTL teams from early design through silicon bring-up. You will evaluate performance, power, and area trade-offs, drive architectural decisions with data, and help define DV-friendly features.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8+ years architecting I/O and system subsystems with hardware/software interfaces.
• Experience with PCIe data link protocols and TLP formats.
• Experience with I/O virtualization technologies such as SR-IOV/SIOV.
• Experience with PCIe capabilities like AER, Downstream Port Containment, and encryption.
• Experience with on-chip scheduling, QoS mechanisms, and latency/bandwidth tradeoffs.
• Experience with cryptography concepts and inline data encryption.
• Experience with x86/ARM architecture, virtualization, IOMMUs, and interrupt virtualization.
• Experience with data center workloads and I/O characteristics.
• Ability to drive architectural decisions independently and data-driven.

Responsibilities

• Own the I/O subsystem architecture for DPUs including PCIe, DMA, offload engines, I/O virtualization, confidential computing, and system management.
• Decide what runs in hardware vs firmware vs host software and design interfaces between them.
• Define hardware/software interface models, descriptors, and offload interfaces for firmware and drivers.
• Collaborate closely with firmware, driver, and software teams to keep interfaces clean and usable.
• Back decisions with performance data and trading off power, area, and performance.
• Coordinate with design, DV, and PD teams on feature definition and PPA tradeoffs.
• Refine architecture to meet design and PD constraints and ease DV complexity.
• Support post-silicon bring-up of the I/O subsystem and resolve interface issues.

Skills

DPU IO Architecture

PCIe & DMA interfaces

I/O virtualization

Hardware-software interface design

Register/Programming models

Offload interfaces

Performance/PPA tradeoffs

System architecture (x86/ARM)

Confidential Computing concepts

Data center IO characterization

Education

Bachelor's degree in Computer Science or Computer Engineering

PhD in Computer Science/Engineering (preferred)

Tools

SystemVerilog

VHDL

Python

Simulation environments

Job description

Meta is seeking a Data Processing Unit (DPU) IO Architect to own the I/O subsystem, PCIe, DMA, offload engines, and I/O virtualization for DPUs and NICs. You will define register and programming models, interfaces, and how hardware, firmware, and software interact.

You will work with firmware, driver, and RTL teams from early design through silicon bring-up. You will evaluate performance, power, and area trade-offs, drive architectural decisions with data, and help define DV-friendly features.