DPU RAS & Debug Architect — Reliability by Design

Meta; Sunnyvale (CA); On-site; USD 170,000 - 260,000; Full time

Job summary

Meta is seeking a DPU RAS and Debug Architect to define reliability, availability, and serviceability architecture for our DPUs. You will set FIT-rate targets, budget them, and decide how errors are detected, corrected, and surfaced to firmware and host software.

You will define the trace, debug, and telemetry infrastructure supporting post-silicon and software/firmware debugging across hardware, firmware, and RTL teams, guiding bring-up from early path-finding through silicon validation.

Qualifications

• Own the RAS and debug architecture for our DPUs.
• Set FIT-rate targets and budget them across memories, logic, interfaces and links.
• Define error detection, correction, reporting, containment and surface to firmware/host software.
• Define trace, debug and performance-monitoring architecture for post-silicon debug and software/firmware debugging.

Responsibilities

• Own the RAS and debug architecture for our DPUs - error detection, correction, and reporting, FIT budgeting, and the trace, debug, and telemetry infrastructure - from early path-finding through silicon bring-up
• Set FIT-rate targets from the intended usages and deployment models, and budget them across design components
• Define the error detection, correction, reporting, and containment architecture and how errors are surfaced to firmware, host software, and platform management
• Define the trace, debug, and performance-monitoring architecture for post-silicon debug and for software/firmware debugging - on-chip trace, telemetry, crash capture, and JTAG model

Skills

RAS architecture

Debug architecture

FIT budgeting

Post-silicon debugging

Hardware-software coordination

Telemetry

JTAG

Tools

JTAG

Telemetry

Post-silicon debugging tools

Job description

Meta is seeking a DPU RAS and Debug Architect to define reliability, availability, and serviceability architecture for our DPUs. You will set FIT-rate targets, budget them, and decide how errors are detected, corrected, and surfaced to firmware and host software.

You will define the trace, debug, and telemetry infrastructure supporting post-silicon and software/firmware debugging across hardware, firmware, and RTL teams, guiding bring-up from early path-finding through silicon validation.