Senior Verification Architect — Lead Design Engineer

Cadence; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Cadence is seeking a verification leader to drive strategy, architecture, and execution across DV efforts. The role focuses on scalable testbench design, rigorous coverage, and collaboration with design, architecture, and emulation teams.

You will mentor junior engineers and own critical verification milestones. The ideal candidate will have 4–7 years in DV for semiconductor/ASIC/SoC, with a strong background in UVM/SystemVerilog and formal methods.

Qualifications

• 4–7 years of hands‑on DV experience in semiconductor/ASIC/SoC companies.
• Bachelor’s or Master’s degree in Electronics/VLSI or related field.

Responsibilities

• Strategy and Architecture: Define verification strategy and methodology, tools, and infrastructure.
• Testbench Architecture: Design scalable, reusable verification environments with BFMs, monitors, scoreboards, checkers.
• Feature Extraction: Identify critical features and corner cases from architectural specs.
• Execution and Technical Leadership: Develop complex test cases and sequences; lead debug efforts with design engineers.
• Constraint Random Testing: Implement constrained‑random stimulus generation.
• Formal Verification: Use formal tools to prove properties and find deep bugs.
• Metric Management: Analyze coverage and oversee GLS simulations.
• Sign‑off: Define done criteria and provide final verification approval.
• Mentorship: Guide junior engineers on coding standards and debugging techniques.
• Cross‑functional Collaboration: Act as technical lead between design, architecture, and emulation teams.
• Project Management: Manage timelines, risks, and priorities to meet deadlines.

Skills

DV experience

Leadership

Cross-functional collaboration

Mentorship

Project management

Debugging

Education

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field

Tools

UVM/SystemVerilog

Formal verification tools

GLS

Job description

Cadence is seeking a verification leader to drive strategy, architecture, and execution across DV efforts. The role focuses on scalable testbench design, rigorous coverage, and collaboration with design, architecture, and emulation teams.

You will mentor junior engineers and own critical verification milestones. The ideal candidate will have 4–7 years in DV for semiconductor/ASIC/SoC, with a strong background in UVM/SystemVerilog and formal methods.