Digital Verification Engineer - UVM/RTL Specialist

Mindlance; San Diego (CA); Vor Ort; USD 90.000 - 120.000; Vollzeit

Zusammenfassung

A national recruiting company is seeking an experienced verification engineer with at least 3 years of experience in Object-Oriented SystemVerilog principles using UVM methodologies. The ideal candidate will have extensive hands-on experience in verifying digital blocks, building UVM based test benches, and debugging RTL & gate-level simulations. A Bachelor's in Electrical Engineering is preferred. This role involves high quality verification and participation in multiple tapeouts.

Qualifikationen

• 3 years minimum experience with Object-Oriented SystemVerilog principles.
• Extensive experience in verifying digital blocks and building UVM based TB.
• Experience in debugging RTL & gate-level simulations.

Aufgaben

• Verify digital blocks using UVM principles.
• Build UVM based test benches and write UVM sequences.
• Participate in multiple tapeouts with high quality verification.

Kenntnisse

Object-Oriented SystemVerilog principles

UVM/OVM/VMM methodologies

Verifying digital blocks

Debugging RTL & gate-level simulations

Ausbildung

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Jobbeschreibung

A national recruiting company is seeking an experienced verification engineer with at least 3 years of experience in Object-Oriented SystemVerilog principles using UVM methodologies. The ideal candidate will have extensive hands-on experience in verifying digital blocks, building UVM based test benches, and debugging RTL & gate-level simulations. A Bachelor's in Electrical Engineering is preferred. This role involves high quality verification and participation in multiple tapeouts.