Digital Verification Engineer: Mixed-Signal & RTL Expert

Talent 101, Inc; Tucson (AZ); On-site; USD 120,000 - 180,000; Full time

Job summary

Talent 101 is seeking an experienced Digital Design Verification Engineer to support mixed-signal semiconductor devices where small digital blocks operate with analog circuitry. The role requires strong SystemVerilog verification experience and the ability to interpret incomplete requirements through collaboration with analog designers.

You will develop verification plans, maintain the DV environment, and run regressions across RTL and gate-level simulations.

Qualifications

• Hands-on digital design verification experience for ASIC, mixed-signal IC, or semiconductor designs.
• Strong SystemVerilog verification experience.
• Ability to learn and modify an existing verification environment.

Responsibilities

• Learn and understand an existing SystemVerilog-based digital verification environment and its architecture.
• Review and execute test cases from previous projects.
• Develop a comprehensive testcase list and verification plan for the new device.
• Implement, debug, and maintain the SystemVerilog verification testcase suite.
• Verify small digital blocks used for test-mode communication, memory programming, and configuration.
• Work with RTL implemented in VHDL and SystemVerilog.
• Run verification regressions and debug RTL development.

Skills

SystemVerilog

ASIC verification

Mixed-signal verification

RTL reading (SV/VHDL)

Debugging & waveform analysis

Tools

SystemVerilog

VHDL

SDF back-annotation

UVM

Job description

Talent 101 is seeking an experienced Digital Design Verification Engineer to support mixed-signal semiconductor devices where small digital blocks operate with analog circuitry. The role requires strong SystemVerilog verification experience and the ability to interpret incomplete requirements through collaboration with analog designers.

You will develop verification plans, maintain the DV environment, and run regressions across RTL and gate-level simulations.