Digital ASIC Verification Engineer

InvestedintheMission; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Stock options

Employee Stock Purchase Plan

Medical coverage

Job summary

SpaceX seeks a motivated Design Verification Engineer to verify digital ASICs used in Starlink satellites and ground infrastructure. You will write test plans, build SystemVerilog testbenches, and drive regressions and coverage to completion.

Ideal candidates have hands-on experience with UVM, Python, and MATLAB, plus a strong coding mindset. The role demands flexibility for extended hours and a collaborative, fast-paced space tech environment.

Qualifications

• Bachelors degree in electrical engineering, computer science or computer engineering.
• 1+ years of experience with design verification and test bench development.
• Strong problem solving and coding skills.
• Experience with verification methodologies such as UVM.

Responsibilities

• Responsible for digital ASIC verification at block and system level.
• Write and review test plans, develop test harnesses and test sequences.
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks.
• Responsible for test plan execution, running regressions, code and functional coverage closure.
• Automate test case generation by using Python and MATLAB programs.
• Contribute towards pre-silicon verification, chip bring‑up and post-silicon validation.
• Be a hands‑on self‑starter who can execute the steps required to fully verify a complex digital designs.

Skills

Design verification

Test bench development

Object‑oriented programming

Problem solving

Python scripting

MATLAB scripting

Constrained random verification

RTL/ASIC verification

Education

Bachelor's degree in electrical engineering, computer science or computer engineering

Advanced degree in electrical/computer engineering

Tools

SystemVerilog

UVM

Python

MATLAB

Job description

SpaceX seeks a motivated Design Verification Engineer to verify digital ASICs used in Starlink satellites and ground infrastructure. You will write test plans, build SystemVerilog testbenches, and drive regressions and coverage to completion.

Ideal candidates have hands-on experience with UVM, Python, and MATLAB, plus a strong coding mindset. The role demands flexibility for extended hours and a collaborative, fast-paced space tech environment.