Digital ASIC Verification Engineer (SystemVerilog/UVM)

SpaceX; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Stock options

401(k) retirement plan

Health insurance

Paid time off (3 weeks)

Job summary

SpaceX designs and tests next-generation ASICs for SpaceX satellites and ground systems. The role focuses on digital ASIC verification at block and system levels, with responsibilities spanning test plan creation, testbench development, and regression execution to ensure robust post-silicon validation.

Ideal candidates have a strong background in SystemVerilog, UVM, and Python for automation, plus experience with RTL and constrained random verification in a dynamic aerospace environment.

Qualifications

• Bachelor’s degree in electrical engineering, computer science or computer engineering.
• 1+ years of experience with design verification and test bench development.
• Experience with verification methodologies such as UVM.
• Strong problem-solving and coding skills.
• Experience with scripting languages, e.g. Python for automation.
• RTL design, chip bring-up, and post-silicon validation experience.

Responsibilities

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

Skills

Design verification

Test bench development

UVM

Python scripting

Object-oriented programming

Constrained random verification

RTL verification

Education

Bachelor’s degree in electrical engineering, computer science or computer engineering

Tools

MATLAB

SystemVerilog

Job description

SpaceX designs and tests next-generation ASICs for SpaceX satellites and ground systems. The role focuses on digital ASIC verification at block and system levels, with responsibilities spanning test plan creation, testbench development, and regression execution to ensure robust post-silicon validation.

Ideal candidates have a strong background in SystemVerilog, UVM, and Python for automation, plus experience with RTL and constrained random verification in a dynamic aerospace environment.