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SpaceX in the United States is seeking a motivated Design Verification Engineer (Silicon Engineering) to join the Starlink project. You will verify digital ASICs at block and system level, write test plans, and develop testbenches using SystemVerilog (UVM and non‑UVM) to validate designs, including DSP blocks.
The role requires a BE/CE/EE degree and 1+ years of verification experience; preferred advanced degree, scripting with Python, MATLAB, and experience with coverage models.
SpaceX in the United States is seeking a motivated Design Verification Engineer (Silicon Engineering) to join the Starlink project. You will verify digital ASICs at block and system level, write test plans, and develop testbenches using SystemVerilog (UVM and non‑UVM) to validate designs, including DSP blocks.
The role requires a BE/CE/EE degree and 1+ years of verification experience; preferred advanced degree, scripting with Python, MATLAB, and experience with coverage models.