Senior ASIC Verification Engineer – Silicon & System-Level

InvestedintheMission; Redmond (WA); On-site; USD 165,000 - 260,000; Full time

Benefits offered by this job

Stock options

Long-term cash awards

Employee Stock Purchase Plan

Medical, vision, and dental coverage

401(k) retirement plan

Disability insurance

Life insurance

Paid parental leave

Paid vacation

Paid holidays

Sick leave

Job summary

SpaceX is seeking a Senior ASIC Design Verification Engineer (Silicon Engineering) to drive digital verification across block and system levels for Starlink ASICs. You will write plans, develop harnesses, run regressions, and close coverage while contributing to pre-silicon bring-up and post-silicon validation.

Expect a fast-paced, collaborative environment with ownership of critical verification milestones.

Qualifications

• Bachelor’s degree in electrical engineering or computer engineering is required.
• 5+ years of experience with design verification and test bench development is required.
• Experience with verification methodologies such as UVM/OVM/VMM.
• Strong object‑oriented programming knowledge.
• Experience in constrained random verification.

Responsibilities

• Responsible for digital ASIC verification at block and system level.
• Write and review test plans, develop test harnesses and test sequences.
• Responsible for test plan execution, running regressions, code and functional coverage closure.
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation.
• Be a hands on self‑starter who can execute the steps required to fully verify a complex digital designs.

Skills

UVM/OVM/VMM

Object-oriented programming

Constrained random verification

Python automation

Test plans

Code coverage

Post-silicon validation

Education

Bachelor's degree in Electrical or Computer Engineering

Advanced degree in Electrical or Computer Engineering

Job description

SpaceX is seeking a Senior ASIC Design Verification Engineer (Silicon Engineering) to drive digital verification across block and system levels for Starlink ASICs. You will write plans, develop harnesses, run regressions, and close coverage while contributing to pre-silicon bring-up and post-silicon validation.

Expect a fast-paced, collaborative environment with ownership of critical verification milestones.