Engineer II - Digital ASIC Design

FHLB Des Moines; San Jose (CA); Hybrid; USD 70,000 - 143,000; Full time

Benefits offered by this job

Health benefits from day one

ESP P program with 2 year look back

Job summary

Microchip Technology Inc. in San Jose seeks an Engineer II to drive RTL implementation of digital IP blocks, focusing on power, performance, and area targets.

You will translate architectural concepts into SystemVerilog, work with SoC teams, and collaborate with Physical Design to resolve timing and routing challenges. The role requires 2.5–5 years in ASIC/FPGA digital design, a BS in Electrical Engineering, and proficiency in SystemVerilog and Cadence/Synopsys flows.

Qualifications

• 2.5–5 years of proven experience in ASIC or FPGA digital design.
• BS degree in Electrical Engineering.
• Proficiency in SystemVerilog and design techniques.
• Experience with front-end EDA flows (Cadence/Synopsys).
• Familiarity with PHY/Serdes protocols is a plus.

Responsibilities

• Follow the micro-architecture and implement RTL (SystemVerilog) of complex digital IP blocks from concept to delivery.
• Drive Power, Performance and Area trade-offs to meet targets.
• Collaborate with SoC teams to ensure seamless connectivity and timing.
• Lead Lint, CDC, RDC, and formal verification efforts.
• Record design activities and cooperate with Physical Design teams to close timing.

Skills

SystemVerilog

ASIC design

Post-silicon validation

Scripting for efficiency

Education

BS in Electrical Engineering

Tools

VCS

SpyGlass

Design Compiler

PrimeTime

Job description

## Engineer II - Digital ASIC DesignApply: CA - San Jose - Fortune Dr (Micrel R&D): Full time: Posted Today: R4031-26Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the *Aggregate System* and it’s won us countless awards for diversity and workplace excellence.Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.Visit our careers page to see what exciting opportunities and company perks await!**Job Description:*** Follow the micro-architecture and implement RTL (System Verilog) of complex digital IP blocks from concept to delivery.* Drive Power, Performance, and Area trade-offs and optimizations to meet aggressive product targets.* Collaborate with SoC integration teams to ensure seamless connectivity and address top-level timing/congestion issues.* Lead Lint, CDC, RDC, and formal verification efforts. Work closely with Physical Design teams to close timing and resolve routing bottlenecks.* Cooperate with teams to verify and validate module and system functions.* Organize documents to record design activities.**Requirements/Qualifications:*** 2.5 - 5 years of proven experience in ASIC or FPGA digital design.* BS degree in Electrical Engineering* Proficiency in System Verilog and a deep understanding of synchronous/asynchronous design techniques.* Experience with the full Cadence/Synopsys front-end EDA flow (e.g., VCS, SpyGlass, Design Compiler, PrimeTime).* Familiarity with PHY or Serdes protocols, knowledge of IEEE 802.3 is a plus* Skillful in scripts to aid efficiency* Post-silicon validation or bring-up experience. Proficient in lab equipment (e.g., oscilloscope, logic analyzer, ..., etc.)**Travel Time:**0% - 25%**Physical Attributes:**Carrying, Feeling, Handling, Hearing, Seeing, Talking, Works Alone, Works Around Others**Physical Requirements:**regular business hours; 70% sitting, 15% standing, 15% walking**Pay Range:**We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:Benefits of working at MicrochipThe annual base salary range for this position, which could be performed in the US, is $70,304 - $143,000.\\*\\*Range is dependent on numerous factors including job location, skills and experience.Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.**To all recruitment agencies**: *Microchip Technology Inc. **does not** accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.*