Engineer II - Digital ASIC Design

Microchip Technology Inc

San Jose (CA)

On-site

USD 70,000 - 143,000

Full time

2 days ago
Be an early applicant
Application generator

Turn this role into an interview — a resume and cover letter built around what this employer wants.

Get past ATS filters

Benefits offered by this job

Health benefits from day one
Retirement savings plan
ESPP with 2-year lookback

Job summary

Microchip Technology Inc is seeking an experienced ASIC/FPGA digital design engineer in the US to implement RTL (SystemVerilog) for complex digital IP blocks, driving PPA trade-offs and collaborating with SoC teams to ensure connectivity and timing targets.

You will lead lint/CDC/RDC and formal verification, work with Physical Design to close timing, and document design activities while applying scripting to improve efficiency and bring-up experiences with test equipment.

Qualifications

  • BS degree in Electrical Engineering.
  • 2.5 - 5 years of proven experience in ASIC or FPGA digital design.
  • Proficiency in System Verilog and a deep understanding of synchronous/asynchronous design techniques.
  • Experience with the full Cadence/Synopsys front-end EDA flow (e.g., VCS, SpyGlass, Design Compiler, PrimeTime).
  • Familiarity with PHY or Serdes protocols, knowledge of IEEE 802.3 is a plus.
  • Skillful in scripts to aid efficiency.
  • Post-silicon validation or bring-up experience. Proficient in lab equipment (e.g., oscilloscope, logic analyzer, ..., etc.)

Responsibilities

  • Follow the micro-architecture and implement RTL (System Verilog) of complex digital IP blocks from concept to delivery.
  • Drive Power, Performance, and Area trade-offs and optimizations to meet aggressive product targets.
  • Collaborate with SoC integration teams to ensure seamless connectivity and address top-level timing/congestion issues.
  • Lead Lint, CDC, RDC, and formal verification efforts. Work closely with Physical Design teams to close timing and resolve routing bottlenecks.
  • Cooperate with teams to verify and validate module and system functions.
  • Organize documents to record design activities.

Skills

SystemVerilog
ASIC/FPGA design
Scripting
PHY/Serdes
Post-silicon validation

Education

BS in Electrical Engineering

Tools

VCS
SpyGlass
Design Compiler
PrimeTime

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:
  • Follow the micro-architecture and implement RTL (System Verilog) of complex digital IP blocks from concept to delivery.
  • Drive Power, Performance, and Area trade-offs and optimizations to meet aggressive product targets.
  • Collaborate with SoC integration teams to ensure seamless connectivity and address top-level timing/congestion issues.
  • Lead Lint, CDC, RDC, and formal verification efforts. Work closely with Physical Design teams to close timing and resolve routing bottlenecks.
  • Cooperate with teams to verify and validate module and system functions.
  • Organize documents to record design activities.
Requirements/Qualifications:
  • 2.5 - 5 years of proven experience in ASIC or FPGA digital design.
  • BS degree in Electrical Engineering
  • Proficiency in System Verilog and a deep understanding of synchronous/asynchronous design techniques.
  • Experience with the full Cadence/Synopsys front-end EDA flow (e.g., VCS, SpyGlass, Design Compiler, PrimeTime).
  • Familiarity with PHY or Serdes protocols, knowledge of IEEE 802.3 is a plus
  • Skillful in scripts to aid efficiency
  • Post-silicon validation or bring-up experience. Proficient in lab equipment (e.g., oscilloscope, logic analyzer, ..., etc.)
Travel Time:

0% - 25%

Physical Attributes:

Carrying, Feeling, Handling, Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

regular business hours; 70% sitting, 15% standing, 15% walking

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position, which could be performed in the US, is $70,304 - $143,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to Know Your Rights: Workplace Discrimination is Illegal Poster.

To all recruitment agencies

Microchip Technology Inc does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Engineer II - Digital ASIC Design
Engineer II - Digital ASIC Design

Microchip Technology Inc. • San Jose (CA)

On-site
USD 70,000 - 143,000
Engineer II - Design
Engineer II - Design

Microchip Technology Inc. • Hauppauge (NY)

On-site
USD 70,000 - 143,000
Health benefits from day one
ESPP program with 2-year lookback
Retirement savings plans
Engineer II - Digital ASIC Design
Engineer II - Digital ASIC Design

FHLB Des Moines • San Jose (CA)

Hybrid
USD 70,000 - 143,000
Health benefits from day one
ESP P program with 2 year look back
Senior Engineer I- Design
Senior Engineer I- Design

Microchip Technology Inc. • Chandler (AZ)

On-site
USD 110,000 - 150,000
Technical Staff Engineer - Applications
Technical Staff Engineer - Applications

Microchip Technology Inc. • Hauppauge (NY)

On-site
USD 91,000 - 232,000
Health benefits day one
ESPP program
Retirement plan
Engineer I - Analog Design
Engineer I - Analog Design

Microchip Technology Inc. • San Jose (CA)

On-site
USD 69,000 - 128,000
Senior FPGA/SoC Applications Engineer
Senior FPGA/SoC Applications Engineer

Microchip Technology Inc. • Addison (TX)

On-site
USD 91,000 - 232,000
Restricted stock units
Quarterly bonus payments
Health benefits from day one
+1
Technical Staff Engineer-Design (Digital Logic)
Technical Staff Engineer-Design (Digital Logic)

Microchip Technology Inc. • Hauppauge (NY)

On-site
USD 91,000 - 232,000
Health benefits starting day one
Retirement savings plans
Quarterly bonuses
Technical Staff Engineer - Design (FPGA Fabric)
Technical Staff Engineer - Design (FPGA Fabric)

Microchip Technology Inc. • San Jose (CA)

On-site
USD 91,000 - 232,000
Technical Staff Engineer-Design (Digital Logic)
Technical Staff Engineer-Design (Digital Logic)

Microchip Technology Inc. • Colorado Springs (CO)

On-site
USD 91,000 - 232,000
Competitive base pay
Restricted stock units
Quarterly bonus payments
+3