RTL & ASIC Design Engineer II

Microchip Technology Inc; Allentown (Lehigh County); On-site; USD 85,000 - 125,000; Full time

Job summary

Microchip Technology Inc is seeking an engineer to design, simulate, and verify RTL-based blocks for SOC devices. You will work on high-speed data paths and protocol interfaces, contributing to timing analysis and verification across multiple IP blocks.

The role requires 2–5 years in RTL design for ASICs, a relevant Bachelor's degree, and strong SystemVerilog skills. On-site opportunities in the Allentown area are available with a focus on collaboration and delivery.

Qualifications

• 2–5 years of experience in RTL Design for ASIC implementation.
• Bachelor's in Electrical Engineering, Computer Engineering or Computer Science.
• Proficiency in SystemVerilog and RTL design methodologies.

Responsibilities

• Design, simulate, and verify RTL-based blocks for SOC devices.
• Participate in RTL implementation, synthesis, simulation, pre-layout/post-layout timing verification.
• Support porting the design into test chips and emulation platforms; FPGA/tools experience is a plus.

Skills

RTL Design

SystemVerilog

ASIC/SoC

Scripting (TCL/Perl/Python)

Linux

FSM/Datapath Design

Education

Bachelor's in Electrical Engineering, Computer Engineering or Computer Science

Master's preferred

Tools

SystemVerilog simulators

Synthesis tools

Formal verification tools

Job description

Microchip Technology Inc is seeking an engineer to design, simulate, and verify RTL-based blocks for SOC devices. You will work on high-speed data paths and protocol interfaces, contributing to timing analysis and verification across multiple IP blocks.

The role requires 2–5 years in RTL design for ASICs, a relevant Bachelor's degree, and strong SystemVerilog skills. On-site opportunities in the Allentown area are available with a focus on collaboration and delivery.