ASIC Digital Design Implementation Engineer

Xoriant US Staffing; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Xoriant US Staffing is seeking a Digital Design Implementation Engineer to join our team. You will work on taking digital designs for wireless systems and high‑speed PHY from RTL to signoff-quality silicon, collaborating with RTL, DFT, and physical design teams.

Responsibilities include ASIC implementation (logic synthesis, STA, PnR), timing signoff, and driving PPA closure, with support for silicon bring‑up and commercialization. Strong EDA tooling experience is required.

Qualifications

• B.S./B.E. in Electrical or Computer Engineering or related field
• 2+ years of ASIC design implementation experience (STA, synthesis or PnR)
• Solid understanding of digital design, timing concepts and constraints
• Scripting skills (Tcl, Python, Perl, or shell)
• Strong teamwork and communication skills
• Experience with high-speed designs (SerDes/PHY) a plus
• Familiarity with low-power design (UPF) and signoff checks (physical verification, IR/EM)

Responsibilities

• Perform ASIC design implementation in one or more of STA, synthesis, or PnR
• Develop and maintain implementation flows and scripts; drive timing, power, and area closure
• Perform timing signoff, including constraint development and checking; resolve timing violations
• Collaborate with RTL, DFT, and physical design teams to resolve implementation issues
• Support silicon bring-up and commercialization

Skills

ASIC design implementation

Logic synthesis

Timing concepts & constraints

Scripting Tcl/Python/Perl

Teamwork & communication

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Synopsys Design Compiler/Fusion Compiler/PrimeTime

Cadence Genus/Innovus/Tempus

Job description

Client is seeking a talented, highly motivated individual to join our team as a Digital Design Implementation Engineer.

You will work as part of a team taking digital designs for wireless communication systems and high-speed PHY from RTL to signoff-quality silicon.

JOB RESPONSIBILITIES

• Perform ASIC design implementation in one or more of: logic synthesis, static timing analysis (STA), and place and route (PnR).
• Develop and maintain implementation flows and scripts, and drive timing, power, and area (PPA) closure.
• Perform timing signoff, including constraint (SDC) development and checking, and resolve timing violations.
• Work with RTL design, DFT, and physical design teams to resolve implementation issues.
• Support silicon bring-up and commercialization.

Requirements

REQUIRED SKILLS

• BS or BE minimum in Electrical/Computer Engineering or a related field, with 2+ years of ASIC design implementation experience in at least one of STA, synthesis, or PnR
• Hands-on experience with industry-standard EDA tools (for example Synopsys Design Compiler/Fusion Compiler/PrimeTime, or Cadence Genus/Innovus/Tempus)
• Solid understanding of digital design, timing concepts, and constraints
• Proficiency in scripting (Tcl, Python, Perl, or shell)
• Teamwork, dedication, strong communications and interpersonal skills
• Excellent communication skills both written and verbal PREFERRED SKILLS
• Experience implementing high-speed designs, such as SerDes/high-speed PHY or high-frequency digital blocks
• Experience with advanced process nodes, clock tree synthesis, and multi-corner/multi-mode (MCMM) timing closure
• Familiarity with low‑power design methodology (UPF) and signoff checks (physical verification, IR/EM)