Digital ASIC Architect - Optical Link & Calibration

Avicena Tech; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Avicena Tech is seeking a Digital Architect to define the digital architecture of a high-speed parallel optical link ASIC. You will shape the data path, link management and calibration engines that drive analog circuits, translating system requirements into SCR/RTL-ready specifications for RTL, verification and firmware teams.

You will lead architecture studies, define interfaces and clocking, and collaborate across design teams to ensure efficient, power-aware implementations and successful

Qualifications

• 12+ years of digital ASIC design experience.
• 5+ years defining architecture or micro-architecture for production chips.
• Strong SystemVerilog/Verilog background and timing/power knowledge.
• Modeling experience in C/C++ or Python; multi-clock design and CDC/RDC.

Responsibilities

• Define digital architecture and micro-architecture specs for the data path and control of a parallel optical link ASIC.
• Architect calibration, training and adaptation engines for analog/mixed-signal parameters.
• Define interfaces, timing and clocking with system architect and leads.
• Create register map and host control interface with firmware team.
• Lead performance, latency, area and power trade-off studies.
• Develop architecture models in C/C++, Python or SystemC for validation and reference data.
• Review RTL and verification plans for alignment with architecture.

Skills

Digital ASIC design

Architecture definition

SystemVerilog/Verilog

C/C++/Python

Multi-clock design

CDC/RDC architecture

High-speed link design

Calibration/control

Education

BS or MS in Electrical or Computer Engineering

Tools

SystemVerilog/Verilog

C/C++

Python

SystemC

Job description

Avicena Tech is seeking a Digital Architect to define the digital architecture of a high-speed parallel optical link ASIC. You will shape the data path, link management and calibration engines that drive analog circuits, translating system requirements into SCR/RTL-ready specifications for RTL, verification and firmware teams.

You will lead architecture studies, define interfaces and clocking, and collaborate across design teams to ensure efficient, power-aware implementations and successful