Digital Architect

Avicena Tech; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Avicena Tech is seeking a Digital Architect to define the digital architecture of a high-speed parallel optical link ASIC. You will shape the data path, link management and calibration engines that drive analog circuits, translating system requirements into SCR/RTL-ready specifications for RTL, verification and firmware teams.

You will lead architecture studies, define interfaces and clocking, and collaborate across design teams to ensure efficient, power-aware implementations and successful

Qualifications

• 12+ years of digital ASIC design experience.
• 5+ years defining architecture or micro-architecture for production chips.
• Strong SystemVerilog/Verilog background and timing/power knowledge.
• Modeling experience in C/C++ or Python; multi-clock design and CDC/RDC.

Responsibilities

• Define digital architecture and micro-architecture specs for the data path and control of a parallel optical link ASIC.
• Architect calibration, training and adaptation engines for analog/mixed-signal parameters.
• Define interfaces, timing and clocking with system architect and leads.
• Create register map and host control interface with firmware team.
• Lead performance, latency, area and power trade-off studies.
• Develop architecture models in C/C++, Python or SystemC for validation and reference data.
• Review RTL and verification plans for alignment with architecture.

Skills

Digital ASIC design

Architecture definition

SystemVerilog/Verilog

C/C++/Python

Multi-clock design

CDC/RDC architecture

High-speed link design

Calibration/control

Education

BS or MS in Electrical or Computer Engineering

Tools

SystemVerilog/Verilog

C/C++

Python

SystemC

Job description

Job Title

Digital Architect

About The Role

Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a Digital Architect to define the digital architecture of our link ASIC: the data path, link management, and the calibration and training engines that control the analog circuits. You will turn system requirements into clear specifications that the RTL, verification and firmware teams can build from.

Key Responsibilities

• Define digital architecture and micro-architecture specifications for the data path, link management and control functions of a parallel optical link ASIC.
• Architect calibration, training and adaptation engines that set and track analog circuit parameters, and partition functions between hardware and firmware.
• Define analog/digital interfaces, timing and control loops with the system architect and the TX, RX and clocking leads.
• Define the register map and host control interface with the firmware team.
• Lead performance, latency, area and power trade-off studies.
• Develop architecture models in C/C++, Python or SystemC to validate algorithms and generate reference data for verification.
• Define clocking, reset and clock-domain-crossing architecture with the implementation team.
• Review RTL and verification plans for alignment with the architecture, and support DFT architecture.
• Support post-silicon bring-up of digital features.

Qualifications

Required

• BS or MS in Electrical or Computer Engineering with 12+ years of digital ASIC design, including 5+ years defining architecture or micro-architecture for production chips.
• Deep experience with high-speed link digital design: framing, encoding and scrambling, error detection or FEC, lane deskew and alignment, and link training.
• Experience architecting digital control and calibration for analog/mixed-signal circuits.
• Strong SystemVerilog/Verilog background and understanding of synthesis, timing and power implications.
• Modeling experience in C/C++ or Python.
• Multi-clock design and CDC/RDC architecture.

Preferred

• SerDes, die-to-die interfaces (such as UCIe) or optical communication links.
• DSP and adaptation algorithms for communication links.
• Hardware/firmware co-design.
• Low-power architecture.
• Technical leadership of design teams.

Key Competencies

• Systems thinker: connects requirements, algorithms and hardware cost.
• Clear writer: produces specifications others can implement without guessing.
• Collaboration: bridges analog, digital and firmware teams.
• Technical judgment: makes and defends trade-offs with data.