DFT & Test Engineer — Hardware Testability Lead

Celestica; Richardson (TX); On-site; USD 90,000 - 130,000; Full time

Job summary

Celestica, located in Richardson, TX, seeks an experienced DFT/Test Engineer to own testability reviews and coverage modeling within the hardware design flow. You will ensure test point access, boundary scan chains, and debugging access meet DFT rules while coordinating with schematic, layout, software, firmware, and test teams to minimize gaps before layout freeze.

This role emphasizes testability as a core design property, supporting early build debug and ongoing rule improvements.

Qualifications

• Strong technical expertise in Design for Testability (DFT) concepts, checking test point access, boundary scan chains, debug access, and provisioning access.
• Proven hands‑on proficiency with Boundary Scan, ICT, and coverage analysis tooling.
• Solid capability in modeling structural and functional test coverage against coverage standards (e.g., MTRS).
• Excellent collaborative problem‑solving skills to disposition hardware and software findings across multi-disciplinary teams.
• Strong cross‑functional communication skills to work effectively with schematic, layout, software, firmware, and test engineering stakeholders.

Responsibilities

• Design Reviews: Review schematic and layout against the DFT rule set before freeze, raising findings alongside supporting evidence behind the rule.
• Coverage Modeling & Verification: Model structural and functional coverage to report gaps against the MTRS, and verify achieved coverage on the first fixture while recording differences against initial claims.
• Issue Disposition: Collaborate cross-functionally with schematic/layout engineers, software/firmware teams, the program TRL, site test engineering, and the DFT manager to resolve coverage gaps via test point additions, chain corrections, or agreed alternatives.
• Build & Debug Support: Support functional test definition and early build debug in tandem with the Test Readiness Lead (TRL) and on-site test SMEs.
• Continuous Improvement: Propose DFT rule changes derived from test escapes and fixture rework feedback to drive ongoing design standards.
• Ownership & Performance: Own key deliverables—including testability reviews, coverage models against MTRS, DFT findings with formal dispositions, achieved coverage evidence documentation, and rule change proposals. Performance is measured on first-fixture designed-in coverage, pre-freeze closed findings, test escape rates, and repeat findings.

Skills

DFT concepts

Testability review

Cross-functional collaboration

Test coverage modeling

Debug/test equipment

Education

Bachelor’s degree in Electrical Engineering

Tools

Boundary Scan

In-Circuit Testing (ICT)

Job description

Celestica, located in Richardson, TX, seeks an experienced DFT/Test Engineer to own testability reviews and coverage modeling within the hardware design flow. You will ensure test point access, boundary scan chains, and debugging access meet DFT rules while coordinating with schematic, layout, software, firmware, and test teams to minimize gaps before layout freeze.

This role emphasizes testability as a core design property, supporting early build debug and ongoing rule improvements.