DFT Engineer for SoC Test & Validation

Wipro; Santa Clara (CA); On-site; USD 60,000 - 149,000; Full time

Benefits offered by this job

Medical and dental benefits

Disability insurance

Paid time off (sick leave included)

Other paid and unpaid leave options

Job summary

Wipro Limited is seeking a DFX Engineer to lead the VLSI development and design, defining functionalities, architecture, layout and implementation for a client project in advanced SoCs. The role requires 6 to 8 years of experience in DFT/DFX, system-level verification, and tool-driven test methodologies.

Responsibilities include test plan creation, IP/SoC level verification, SystemVerilog/UVM environments, and collaboration with Design, Architecture, Physical Design, and ATE teams.

Qualifications

• Experience with DFX/DFT concepts and verification.
• Knowledge of Scan, ATPG, MBIST/LBIST.
• End-to-end DFX flow experience is a plus.

Responsibilities

• Create and execute test plans for DFX features including Scan, MBIST, SSN, EDT, IJTAG, and JTAG.
• Verify DFX implementations at IP, subsystem, and SoC levels.
• Develop SystemVerilog/UVM based verification environments and test benches.
• Debug regression failures and identify root causes related to design or verification.
• Generate and validate Scan/ATPG patterns for production testing.
• Collaborate with cross-functional teams including Design, Architecture, Physical Design, Validation, and ATE teams.
• Automate DFX flows using scripting languages and improve overall test methodologies.
• Contribute to DFX architecture planning and implementation for next-generation SoCs.

Skills

DFX / DFT

Scan Insertion

ATPG Pattern Generation

MBIST / LBIST

JTAG, IEEE 1500, IEEE 1687

SSN (Streaming Scan Network)

Education

B.E./B.Tech in Electronics/EE/VLSI

Tools

Siemens Tessent Suite

Synopsys Fusion Compiler

Synopsys Design Compiler

SpyGlass

RTL and Gate-Level Simulation Tools

Job description

Wipro Limited is seeking a DFX Engineer to lead the VLSI development and design, defining functionalities, architecture, layout and implementation for a client project in advanced SoCs. The role requires 6 to 8 years of experience in DFT/DFX, system-level verification, and tool-driven test methodologies.

Responsibilities include test plan creation, IP/SoC level verification, SystemVerilog/UVM environments, and collaboration with Design, Architecture, Physical Design, and ATE teams.