DFT Engineer

Wipro; Santa Clara (CA); On-site; USD 60,000 - 149,000; Full time

Benefits offered by this job

Medical and dental benefits

Disability insurance

Paid time off (sick leave included)

Other paid and unpaid leave options

Job summary

Wipro Limited is seeking a DFX Engineer to lead the VLSI development and design, defining functionalities, architecture, layout and implementation for a client project in advanced SoCs. The role requires 6 to 8 years of experience in DFT/DFX, system-level verification, and tool-driven test methodologies.

Responsibilities include test plan creation, IP/SoC level verification, SystemVerilog/UVM environments, and collaboration with Design, Architecture, Physical Design, and ATE teams.

Qualifications

• Experience with DFX/DFT concepts and verification.
• Knowledge of Scan, ATPG, MBIST/LBIST.
• End-to-end DFX flow experience is a plus.

Responsibilities

• Create and execute test plans for DFX features including Scan, MBIST, SSN, EDT, IJTAG, and JTAG.
• Verify DFX implementations at IP, subsystem, and SoC levels.
• Develop SystemVerilog/UVM based verification environments and test benches.
• Debug regression failures and identify root causes related to design or verification.
• Generate and validate Scan/ATPG patterns for production testing.
• Collaborate with cross-functional teams including Design, Architecture, Physical Design, Validation, and ATE teams.
• Automate DFX flows using scripting languages and improve overall test methodologies.
• Contribute to DFX architecture planning and implementation for next-generation SoCs.

Skills

DFX / DFT

Scan Insertion

ATPG Pattern Generation

MBIST / LBIST

JTAG, IEEE 1500, IEEE 1687

SSN (Streaming Scan Network)

Education

B.E./B.Tech in Electronics/EE/VLSI

Tools

Siemens Tessent Suite

Synopsys Fusion Compiler

Synopsys Design Compiler

SpyGlass

RTL and Gate-Level Simulation Tools

Job description

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Job Description

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client

Experience: 6 to 8 yrs

We are looking for a highly motivated DFX Engineer to develop, implement, verify, and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture, Design, Verification, Physical Design, and Post-Silicon teams to ensure robust manufacturability, testability, and silicon quality.

Key Responsibilities

• Create and execute test plans for DFX features including Scan, MBIST, SSN, EDT, IJTAG, and JTAG.
• Verify DFX implementations at IP, subsystem, and SoC levels.
• Develop SystemVerilog/UVM based verification environments and test benches.
• Debug regression failures and identify root causes related to design or verification.
• Generate and validate Scan/ATPG patterns for production testing.
• Collaborate with cross-functional teams including Design, Architecture, Physical Design, Validation, and ATE teams.
• Automate DFX flows using scripting languages and improve overall test methodologies.
• Contribute to DFX architecture planning and implementation for next-generation SoCs.

Required Technical Skills

• DFX / DFT
• Scan Insertion & Compression
• ATPG Pattern Generation & Debug
• MBIST / LBIST
• JTAG, IEEE 1500, IEEE 1687 (IJTAG)
• SSN (Streaming Scan Network)

EDA Tools

• Siemens Tessent Suite (TestKompress, MBIST, SSN, IJTAG, EDT)
• Synopsys Fusion Compiler
• Synopsys Design Compiler
• SpyGlass
• RTL and Gate-Level Simulation Tools

Verification

• SystemVerilog
• UVM
• Assertions (SVA)
• Functional and Code Coverage
• SoC/IP Verification
• Python/Perl, TCL/Shell Scripting

Preferred Qualifications

• Experience in end-to-end DFX flow development.
• Strong understanding of ASIC/SoC design flow from RTL to silicon.
• Exposure to high-speed interfaces such as PCIe, DDR, Ethernet, USB, CXL, UCIe, or SerDes is a plus.

Educational Qualification

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Computer Engineering, or related fields.

Mandatory Skills: VLSI Design For Testability - DFT.Experience: 5-8 Years.The expected compensation for this role ranges from $60,000 to $148,500 .Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.

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We are an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, caste, creed, religion, gender, marital status, age, ethnic and national origin, gender identity, gender expression, sexual orientation, political orientation, disability status, protected veteran status, or any other characteristic protected by law.

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