Wafer-Scale DFT Lead for Advanced SoCs

Conductor; San Francisco, Austin, Boston (CA, TX, MA); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Conductor is seeking DFT engineers to contribute to and own DFT efforts for blocks and entire dies on wafer-scale A-0 and A-1 systems. You will drive test and diagnosis strategies to ensure high yield and robust design for cutting-edge hardware.

Ideal candidates will have experience leading DFT efforts for multiple advanced node SoC tapeouts and will bring expertise in multi-die and multi-chiplet designs, including AI accelerators.

Qualifications

• Experience leading DFT efforts for multiple advanced node SoC tapeouts.
• Strong background in DFT concepts and methodologies.

Responsibilities

• Contribute to and own DFT efforts for blocks and entire dies on wafer-scale systems.

Skills

DFT engineering

Technical leadership

SoC tapeouts

Job description

Conductor is seeking DFT engineers to contribute to and own DFT efforts for blocks and entire dies on wafer-scale A-0 and A-1 systems. You will drive test and diagnosis strategies to ensure high yield and robust design for cutting-edge hardware.

Ideal candidates will have experience leading DFT efforts for multiple advanced node SoC tapeouts and will bring expertise in multi-die and multi-chiplet designs, including AI accelerators.