ASIC/SOC DFT Engineer for Next-Gen Connectivity

Spacex; Palo Alto (CA); On-site; USD 135,000 - 210,000; Full time

Benefits offered by this job

Medical, Vision & Dental

401(k) retirement plan

Paid vacation (3 weeks)

Paid holidays

Parental leave

Stock options

Employee stock purchase plan

Job summary

SpaceX is hiring an ASIC/DFT Engineer (Silicon Engineering) to develop and validate next‑generation ASICs for space and ground infrastructure. You will work with cross‑disciplinary teams to implement scan insertion, DFT fabrics, ATPG content, and verification strategies.

The role emphasizes RTL/DFT readiness, high‑reliability design practices, and collaboration with manufacturing to ensure robust silicon from design to test. SpaceX offers strong compensation and comprehensive benefits.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional experience working with ASICs.
• Experience in scan insertion or DFT setup.

Responsibilities

• Evaluate design readiness for scan insertion through RTL and physical design Scan DRC tools.
• Integrate and verify Design for Test (DFT) fabrics and IP within subsystems.
• Run ATPG analysis to ensure quality scan chain construction and basic coverage goals.
• Perform non-timing and SDF annotated gate-level simulations and debug.
• Create ATPG content for post-silicon testing and verify via gate-level simulation.
• Collaborate with circuit physical design, ATPG and manufacturing teams to improve silicon coverage.

Skills

Scan insertion

DFT setup

Verilog/SystemVerilog

UPF

Scripting (Python)

Formal verification

DRC

Education

Bachelor’s degree in electrical engineering, computer engineering or computer science

Tools

Verilog/SystemVerilog tools

Job description

SpaceX is hiring an ASIC/DFT Engineer (Silicon Engineering) to develop and validate next‑generation ASICs for space and ground infrastructure. You will work with cross‑disciplinary teams to implement scan insertion, DFT fabrics, ATPG content, and verification strategies.

The role emphasizes RTL/DFT readiness, high‑reliability design practices, and collaboration with manufacturing to ensure robust silicon from design to test. SpaceX offers strong compensation and comprehensive benefits.