Principal DFT Engineer - Space-Grade ASICs

InvestedintheMission; Palo Alto (CA); On-site; USD 220,000 - 355,000; Full time

Benefits offered by this job

Stock options

Long-term incentives

Discretionary bonuses

Medical insurance

Vision and dental

401(k) plan

Paid parental leave

Paid vacation

Paid holidays

Disability insurance

Job summary

SpaceX in California seeks a Principal DFT Engineer (Silicon Engineering) to lead the implementation and optimization of DFT architectures for Starlink ASICs, collaborating with systems, firmware, design, validation and ASIC teams.

The role requires ATPG pattern generation, RTL/physical design DRC checks, and integration of DFT fabrics with strong Verilog/SystemVerilog skills and UPF experience. Extended hours may be needed to meet milestones.

Qualifications

• Lead DFT architecture and ATPG pattern design for ASICs.
• Strong RTL/Verilog debugging and verification experience.
• Knowledge of UPF methods and DRC checks required.

Responsibilities

• Lead implementation and optimization of DFT architectures including scan insertion and memory BIST.
• Own ATPG tooling, pattern generation, diagnosis, and post‑silicon validation.
• Evaluate RTL/physical design DRC readiness for scan insertion.
• Integrate DFT fabrics and IPs in subsystems.
• Develop test scripts and automate data analysis with Perl/Python/Tcl/C.
• Collaborate with cross‑functional teams across design, validation, and ASIC execution.

Skills

DFT architectures

ATPG pattern generation

RTL design verification

Verilog/SystemVerilog

Power/clock optimization

UPF/DFT verification

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

Siemens Tessent

Gate-level DFT tools

Job description

SpaceX in California seeks a Principal DFT Engineer (Silicon Engineering) to lead the implementation and optimization of DFT architectures for Starlink ASICs, collaborating with systems, firmware, design, validation and ASIC teams.

The role requires ATPG pattern generation, RTL/physical design DRC checks, and integration of DFT fabrics with strong Verilog/SystemVerilog skills and UPF experience. Extended hours may be needed to meet milestones.