DFT & ASIC Design Intern — AI Hardware

Etched; San Jose (CA); On-site; USD 27,552 - 41,328; Full time

Benefits offered by this job

Generous housing support

Daily lunch and dinner

Direct mentorship from industry leaders

Job summary

A leading AI technology company in San Jose is seeking a DFT Intern for a 12-week paid internship. The role involves reviewing and refining DFT flow automation to support chip-level regression and contributing to various simulations. Ideal candidates should be pursuing a degree in electrical or computer engineering, with familiarity in Verilog or SystemVerilog and ASIC design concepts. The position offers mentoring from industry leaders and generous housing support for those relocating.

Qualifications

• Progress towards relevant degree (Bachelor's, Master's, or PhD).
• Familiarity with hardware description languages.
• Exposure to ASIC design concepts.

Responsibilities

• Review and refine DFT flow automation for chip-level regression.
• Contribute to DFT verification simulations.
• Develop flows for various ATPG fault models.

Skills

Verilog or SystemVerilog

ASIC or SoC design concepts

Digital logic design fundamentals

Scripting in Python or Tcl

Ability to learn quickly

Education

Bachelor's degree in electrical engineering, computer engineering, or related field

Tools

Tessent

Job description

A leading AI technology company in San Jose is seeking a DFT Intern for a 12-week paid internship. The role involves reviewing and refining DFT flow automation to support chip-level regression and contributing to various simulations. Ideal candidates should be pursuing a degree in electrical or computer engineering, with familiarity in Verilog or SystemVerilog and ASIC design concepts. The position offers mentoring from industry leaders and generous housing support for those relocating.