DFT Intern

The Consensus; San Jose (CA); On-site; USD 22,320 - 33,480; Full time

Benefits offered by this job

Housing support

Daily meals in office

Mentorship from engineers

Job summary

Etched is seeking a DFT Intern to help review and refine DFT flow automation for chip-level regression on Caelius. You will collaborate with frontend and backend design teams, contributing to DFT verification (MBIST, Scan, BSCAN, SSN) and developing flows for ATPG fault models.

Summer '26 through Summer '27 internships are offered, with 12-week paid terms, generous housing support for relocations, and daily meals in the office.

Qualifications

• Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with a hardware description language (Verilog or SystemVerilog)
• Exposure to ASIC or SoC design concepts
• Familiarity with digital logic design fundamentals
• Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
• Familiarity with scripting in Python, Tcl, or another language
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Responsibilities

• Review and refine DFT flow automation to support chip-level regression on Caelius
• Work across frontend and backend design teams
• Contribute to DFT verification (MBIST, Scan, BSCAN, and SSN simulations)
• Develop flows for various ATPG fault models

Skills

Degree progress

HDL Verilog/SystemVerilog

ASIC/SoC concepts

Digital logic

ASIC design flow

Python/Tcl scripting

Transformers AI basics

Education

Bachelor's/Master's/PhD in EE/CE

Tools

Tessent or DFT tooling

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

• Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with a hardware description language (Verilog or SystemVerilog)
• Exposure to ASIC or SoC design concepts
• Familiarity with digital logic design fundamentals
• Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
• Familiarity with scripting in Python, Tcl, or another language
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

• Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
• Experience with Tessent or similar DFT tooling
• Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
• Exposure to DFT flow automation or regression infrastructure
• Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

• 12-week paid internship
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Based at our office in San Jose, CA
• Direct mentorship from industry leaders and world-class engineers
• Opportunity to work on one of the most important problems of our time

For any questions, contact [e-mail].

How we’re different

Etched believes in Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.