DFT Intern

Etched; San Jose (CA); On-site; USD 27,552 - 41,328; Full time

Benefits offered by this job

Generous housing support

Daily lunch and dinner

Direct mentorship from industry leaders

Job summary

A leading AI technology company in San Jose is seeking a DFT Intern for a 12-week paid internship. The role involves reviewing and refining DFT flow automation to support chip-level regression and contributing to various simulations. Ideal candidates should be pursuing a degree in electrical or computer engineering, with familiarity in Verilog or SystemVerilog and ASIC design concepts. The position offers mentoring from industry leaders and generous housing support for those relocating.

Qualifications

• Progress towards relevant degree (Bachelor's, Master's, or PhD).
• Familiarity with hardware description languages.
• Exposure to ASIC design concepts.

Responsibilities

• Review and refine DFT flow automation for chip-level regression.
• Contribute to DFT verification simulations.
• Develop flows for various ATPG fault models.

Skills

Verilog or SystemVerilog

ASIC or SoC design concepts

Digital logic design fundamentals

Scripting in Python or Tcl

Ability to learn quickly

Education

Bachelor's degree in electrical engineering, computer engineering, or related field

Tools

Tessent

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment.

You may be a good fit if you have

• Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
• Familiarity with a hardware description language (Verilog or SystemVerilog)
• Exposure to ASIC or SoC design concepts
• Familiarity with digital logic design fundamentals
• Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
• Familiarity with scripting in Python, Tcl, or another language
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

• Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
• Experience with Tessent or similar DFT tooling
• Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
• Exposure to DFT flow automation or regression infrastructure
• Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

• 12-week paid internship (June - August 2026)
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Based at our office in San Jose, CA
• Direct mentorship from industry leaders and world‑class engineers
• Opportunity to work on one of the most important problems of our time

For any questions, contact [e-mail].