DFT Architect for Multi-Chip AI SOCs

Eridu; Saratoga (CA); On-site; USD 195,000 - 250,000; Full time

Job summary

Eridu, a Silicon Valley-based hardware startup, seeks a senior DFT/ASIC engineer to shape the DFT architecture for a multi-chip SOC. You will work on synthesis constraints, LBIST, and advanced test methods in a fast-paced team.

You will apply Verilog/SystemVerilog, deep sub-micron 7nm processes, and EMIB-aware designs to improve test coverage, power, and performance while collaborating across design and verification teams in Saratoga, CA.

Qualifications

• Knowledge of synthesis, DFT & Simulation CAD tools.
• Familiarity with logic & physical design principles for low-power, high-performance designs.
• Fluency in scripting languages: Unix, Perl, Python, TCL.
• Good understanding of device physics; experience with 7nm or below.
• Exposure to EMIB architectures is a plus.
• Knowledge of Verilog and SystemVerilog.
• Strong problem solving, written and verbal communication; highly self-motivated.
• Ability to work in a team under aggressive schedules.
• Prior experience with multiple tape-outs in 7nm or below is required.

Responsibilities

• Define the DFT architecture of a multi-chip system SoC, covering Scan, BIST, Memory Repair, and ACJTAG/DCJTAG.
• Proficiency in Synthesis design constraints (e.g., SDC).
• Prior experience with Serializers/Deserializers.
• Proficiency in Mentor/Synopsys test tools; focus on synthesis.
• Define and implement OCC; exposure to LBIST and streaming tests preferred.
• Fluent RTL and gate-level simulation skills.
• Supervise ATPG generation and achieve high coverage for scan and speed scan.

Skills

DFT & Synthesis tools

Verilog / SystemVerilog

Logic & physical design

Scripting: Unix / Python / Perl / TCL

7nm deep sub-micron tech

EMIB architectures

Problem solving & communication

Team collaboration

Tape-out experience

Education

Master’s or Bachelor’s in EE

Tools

Synthesis CAD tools

Job description

Eridu, a Silicon Valley-based hardware startup, seeks a senior DFT/ASIC engineer to shape the DFT architecture for a multi-chip SOC. You will work on synthesis constraints, LBIST, and advanced test methods in a fast-paced team.

You will apply Verilog/SystemVerilog, deep sub-micron 7nm processes, and EMIB-aware designs to improve test coverage, power, and performance while collaborating across design and verification teams in Saratoga, CA.