Senior DFT Architect - Multi-Chip SOC

Eridu Corp.; Saratoga (CA); On-site; USD 195,000 - 250,000; Full time

Job summary

Eridu Corp., a Silicon Valley hardware startup, seeks a senior EE to define the DFT architecture for a multi-chip SOC, encompassing test design functions such as Scan, BIST, Memory Repair, and advanced DFT techniques.

You will work with a world-class engineering team, require 15+ years of EE experience, fluency in Verilog/SystemVerilog, RTL and gate-level simulation, and proficiency with Mentor or Synopsys test tools. The role is based in Saratoga, CA with a competitive base salary.

Qualifications

• Master’s or EE degree with extensive experience in VLSI/DFT.
• Experience with Verilog/SystemVerilog, RTL and gate-level simulation.
• Knowledge of synthesis constraints and DFT tools (Mentor/Synopsys).

Responsibilities

• Define the DFT architecture of a multi-chip SOC.
• Implement OCC and advanced DFT techniques (LBIST, streaming).
• Supervise ATPG generation and achieve high scan coverage.
• Work with RTL and gate-level simulation to verify designs.

Education

Master’s Degree or bachelor’s degree in EE

Tools

Mentor/Synopsys test tools

Verilog

SystemVerilog

RTL/gate-level simulation

ATPG

Synthesis constraints (SDC)

LBIST/Streaming DFT

Scripting (Unix, Python, TCL, Perl)

Job description

Eridu Corp., a Silicon Valley hardware startup, seeks a senior EE to define the DFT architecture for a multi-chip SOC, encompassing test design functions such as Scan, BIST, Memory Repair, and advanced DFT techniques.

You will work with a world-class engineering team, require 15+ years of EE experience, fluency in Verilog/SystemVerilog, RTL and gate-level simulation, and proficiency with Mentor or Synopsys test tools. The role is based in Saratoga, CA with a competitive base salary.