DFT Engineer

Eridu Corp.; Saratoga (CA); On-site; USD 195,000 - 250,000; Full time

Job summary

Eridu Corp., a Silicon Valley hardware startup, seeks a senior EE to define the DFT architecture for a multi-chip SOC, encompassing test design functions such as Scan, BIST, Memory Repair, and advanced DFT techniques.

You will work with a world-class engineering team, require 15+ years of EE experience, fluency in Verilog/SystemVerilog, RTL and gate-level simulation, and proficiency with Mentor or Synopsys test tools. The role is based in Saratoga, CA with a competitive base salary.

Qualifications

• Master’s or EE degree with extensive experience in VLSI/DFT.
• Experience with Verilog/SystemVerilog, RTL and gate-level simulation.
• Knowledge of synthesis constraints and DFT tools (Mentor/Synopsys).

Responsibilities

• Define the DFT architecture of a multi-chip SOC.
• Implement OCC and advanced DFT techniques (LBIST, streaming).
• Supervise ATPG generation and achieve high scan coverage.
• Work with RTL and gate-level simulation to verify designs.

Education

Master’s Degree or bachelor’s degree in EE

Tools

Mentor/Synopsys test tools

Verilog

SystemVerilog

RTL/gate-level simulation

ATPG

Synthesis constraints (SDC)

LBIST/Streaming DFT

Scripting (Unix, Python, TCL, Perl)

Job description

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

Responsibilities

• Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG).
• Proficiency in Synthesis design constraints. ( Ie SDC)
• Prior experience with Serializers/Deserilizers.
• Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis,
• Define and implement OCC. Exposure to advanced DFT techniques like LBIST and streaming preferred.
• Fluent in RTL level and Gate level simulation.
• Supervise ATPG generation and achieve high coverage goals for scan and @speed scan.

Qualifications

• Knowledge using synthesis, DFT & Simulation CAD tools
• Familiarity with logic & physical design principles to drive low-power & higher-performance designs
• Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL
• Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
• Prior Exposure to EMIB architectures and bridge is a plus.
• Knowledge of Verilog and System Verilog
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
• Ability to work well in a team and be productive under aggressive schedules
• Prior experience of multiple tape out in deep submicron 7nm or below is required.
• Master’s Degree or bachelor’s degree in EE with a minimum of 15+ years of experience.

Why Join Us?

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

Notice to Recruiting Agencies

Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.

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The pay range for this role is:

195,000 - 250,000 USD per year (Saratoga, CA )