DFT Engineer

Eridu; Saratoga (CA); On-site; USD 195,000 - 250,000; Full time

Job summary

Eridu, a Silicon Valley-based hardware startup, seeks a senior DFT/ASIC engineer to shape the DFT architecture for a multi-chip SOC. You will work on synthesis constraints, LBIST, and advanced test methods in a fast-paced team.

You will apply Verilog/SystemVerilog, deep sub-micron 7nm processes, and EMIB-aware designs to improve test coverage, power, and performance while collaborating across design and verification teams in Saratoga, CA.

Qualifications

• Knowledge of synthesis, DFT & Simulation CAD tools.
• Familiarity with logic & physical design principles for low-power, high-performance designs.
• Fluency in scripting languages: Unix, Perl, Python, TCL.
• Good understanding of device physics; experience with 7nm or below.
• Exposure to EMIB architectures is a plus.
• Knowledge of Verilog and SystemVerilog.
• Strong problem solving, written and verbal communication; highly self-motivated.
• Ability to work in a team under aggressive schedules.
• Prior experience with multiple tape-outs in 7nm or below is required.

Responsibilities

• Define the DFT architecture of a multi-chip system SoC, covering Scan, BIST, Memory Repair, and ACJTAG/DCJTAG.
• Proficiency in Synthesis design constraints (e.g., SDC).
• Prior experience with Serializers/Deserializers.
• Proficiency in Mentor/Synopsys test tools; focus on synthesis.
• Define and implement OCC; exposure to LBIST and streaming tests preferred.
• Fluent RTL and gate-level simulation skills.
• Supervise ATPG generation and achieve high coverage for scan and speed scan.

Skills

DFT & Synthesis tools

Verilog / SystemVerilog

Logic & physical design

Scripting: Unix / Python / Perl / TCL

7nm deep sub-micron tech

EMIB architectures

Problem solving & communication

Team collaboration

Tape-out experience

Education

Master’s or Bachelor’s in EE

Tools

Synthesis CAD tools

Job description

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

Responsibilities

• Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG).
• Proficiency in Synthesis design constraints. ( Ie SDC)
• Prior experience with Serializers/Deserilizers.
• Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis,
• Define and implement OCC. Exposure to advanced DFT techniques like LBIST and streaming preferred.
• Fluent in RTL level and Gate level simulation.
• Supervise ATPG generation and achieve high coverage goals for scan and @speed scan.

Qualifications

• Knowledge using synthesis, DFT & Simulation CAD tools
• Familiarity with logic & physical design principles to drive low-power & higher-performance designs
• Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL
• Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
• Prior Exposure to EMIB architectures and bridge is a plus.
• Knowledge of Verilog and System Verilog
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
• Ability to work well in a team and be productive under aggressive schedules
• Prior experience of multiple tape out in deep submicron 7nm or below is required.
• Master’s Degree or bachelor’s degree in EE with a minimum of 15+ years of experience.

Why Join Us?

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

The pay range for this role is:

195,000 - 250,000 USD per year (Saratoga, CA )