Principal Design Verification Architect - CXL/PCIe

Asteralabs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Job summary

Astera Labs seeks a Principal/Senior Principal Design Verification Engineer to lead verification of next‑gen connectivity IPs and SoCs powering AI and cloud infrastructure. You will define verification strategies, mentor teams, and coordinate across architecture, RTL, firmware, and silicon groups to ensure first‑pass silicon success.

The role requires deep expertise in protocol verification and building world‑class verification environments, with strong leadership in planning, coverage, and CI.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• 10+ years (Principal) or 15+ years (Senior Principal) in Design Verification.
• Strong SystemVerilog and UVM expertise.
• Experience with verification planning, execution, sign-off.
• Deep knowledge of constrained-random verification and coverage-driven methodologies.
• Experience with SVA, functional coverage, and protocol compliance.
• Excellent debugging of RTL, simulation, waveform analysis.
• Experience with industry simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.

Responsibilities

• Lead the verification strategy for complex IPs and SoCs from architecture through silicon.
• Define verification methodologies, reusable frameworks, and best practices across programs.
• Drive verification planning, execution, coverage closure, and sign-off.
• Identify verification risks early and drive mitigation plans.
• Lead technical reviews including architecture, RTL, verification, and tape‑out readiness reviews.
• Architect and develop scalable UVM verification environments.
• Develop constrained‑random, coverage‑driven verification methodologies.
• Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models.
• Debug complex RTL, protocol, timing, and integration issues.
• Drive regression planning, automation, and continuous integration improvements.
• Develop reusable VIP and verification infrastructure across multiple product lines.
• Mentor verification engineers and establish verification standards across the organization.

Skills

SystemVerilog

UVM

Verification leadership

Debug RTL

Constrained-random verification

Coverage-driven verification

Python scripting

Emulation prototyping

VIP development

Protocol verification

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

Astera Labs seeks a Principal/Senior Principal Design Verification Engineer to lead verification of next‑gen connectivity IPs and SoCs powering AI and cloud infrastructure. You will define verification strategies, mentor teams, and coordinate across architecture, RTL, firmware, and silicon groups to ensure first‑pass silicon success.

The role requires deep expertise in protocol verification and building world‑class verification environments, with strong leadership in planning, coverage, and CI.