Design Verification Engineer – RTL/UVM for Display

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 150,000 - 225,000; Full time

Benefits offered by this job

Employee stock purchase plan

Restricted stock units (RSU)

Medical and dental coverage

Tuition reimbursement

Job summary

Apple Inc. is seeking a verification engineer to join the Display Technologies team in Cupertino.

You will design and maintain scalable SystemVerilog UVM based test benches for SOC and sub-system verification and collaborate with RTL designers to validate next-generation Apple products. The role involves developing verification strategies, updating environment scripts in Python, and creating coverage models to ensure 100% coverage goals are met.

Qualifications

• Master’s degree in Electrical and Computer Engineering or related field.
• Experience with Verilog/SystemVerilog for testbench development.
• Proven ability to create testplans and coverage plans.
• C/C++ used for reference models or checkers.
• Scripting in Perl, Python, or Tcl for regression automation.
• Knowledge of Digital Electronics and RTL concepts.
• Experience with simulators and waveform viewers.

Responsibilities

• Develop verification strategies and UVM-based test benches.
• Update Python scripts to support new test configurations.
• Create and maintain coverage models and metrics.
• Run RTL and gate-level simulations and analyze failures.
• File bug reports and coordinate with RTL designers.
• Build automated regressions and document test plans.

Skills

Verilog

SystemVerilog

Testbench

Python

C/C++

Debugging

Education

Master’s degree in Electrical and Computer Engineering

Tools

SimVision

Verilog simulators

UVM

Job description

Apple Inc. is seeking a verification engineer to join the Display Technologies team in Cupertino.

You will design and maintain scalable SystemVerilog UVM based test benches for SOC and sub-system verification and collaborate with RTL designers to validate next-generation Apple products. The role involves developing verification strategies, updating environment scripts in Python, and creating coverage models to ensure 100% coverage goals are met.