Design Verification Engineer - SoC & IP Validation

Apple; Cupertino (CA); On-site; USD 174,000 - 225,000; Full time

Job summary

APPLE INC is seeking a senior verification engineer in Cupertino to design and architect verification environments for IPs and SoCs. You will work with design, architecture and software teams to understand use cases, corner conditions and drive robust test cases.

This role emphasizes scalable verification and test bench development. The candidate will apply SystemVerilog/UVM, run RTL simulations with VCS/Xcelium/ModelSim, and use JasperGold for formal checks.

Qualifications

• Master's degree in Electrical Engineering or Computer Engineering with 3 years of related verification experience.
• SystemVerilog and UVM methodology to implement scalable verification environments and test cases.
• RTL/gate-level simulations using VCS, Xcelium or ModelSim.
• Formal verification with JasperGold for connectivity and coverage.
• Coverage tools such as Mentor InFact or Cadence vManager/IMC for code and functional coverage.
• C/C++ functional and performance modeling for verification.
• Computer architecture and digital design knowledge for failure analysis and debugging.
• Waveform debugging with Indago and Verdi; scripting in Perl, Tcl, Python.
• Version control with Perforce, Git and ClearCase.

Responsibilities

• Design and architect verification environments; develop test plans and test benches.
• Collaborate with design, micro-architecture, and software teams to cover use cases and corner conditions.
• Drive test case creation, regression planning, and coverage closure to guarantee IP/SoC quality.
• Communicate results and debug complex functional/performance issues across teams.
• Support design verification lifecycle from planning to final sign-off.

Skills

SystemVerilog

UVM

RTL/Simulation

C/C++

JasperGold

Mentor InFact

Cadence vManager

Perforce

Git

Python

Indago

Verdi

Perl

Tcl

ClearCase

Education

Master's degree in Electrical or Computer Engineering

Tools

VCS

Xcelium

ModelSim

JasperGold

Mentor InFact

Cadence vManager

Indago

Verdi

Git

Perforce

ClearCase

Job description

APPLE INC is seeking a senior verification engineer in Cupertino to design and architect verification environments for IPs and SoCs. You will work with design, architecture and software teams to understand use cases, corner conditions and drive robust test cases.

This role emphasizes scalable verification and test bench development. The candidate will apply SystemVerilog/UVM, run RTL simulations with VCS/Xcelium/ModelSim, and use JasperGold for formal checks.